Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: An encoding method is provided which includes receiving a plurality of images, obtaining values of elements in a portion of the images, sorting the elements according to different values of the elements, sorting the elements according to a number of occurrences of the different values and encoding the elements using a subset of the different values having corresponding numbers of occurrences that are higher than corresponding numbers of occurrences of other values. Examples also include a processing device and method for use with palette mode encoding in which the elements are a portion of pixels in images and the values are color values of the portion of pixels in the images.

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

Abstract: A technique for determining a quality value for a subject block of encoded video is provided. Contributing blocks, of the same frame and/or different frames of the subject block, are determined by identifying blocks likely to be a part of the same moving object or background as the subject block. A spatial and/or temporal filter is then applied to the quality values of the contributing blocks and an initial quality value of the subject block. With a spatial filter, quality values for contributing blocks from the same frame are combined and used to modify the quality value of the subject block. With a spatial filter, a temporal characteristic quality value for contributing blocks of one or more other frames (such as the immediately previous frame) is determined and then combined with a quality value representative of the subject block.

Abstract: Systems, apparatuses, and methods for using a multi-stream foveal display transport layer are disclosed. A virtual reality (VR) system includes a transmitter sending a plurality of streams over a display transport layer to a receiver coupled to a display. Each stream corresponds to a different image to be blended together by the receiver. The images include at least a foveal region image corresponding to a gaze direction of the eye and a background image which is a lower-resolution image with a wider field of view than the foveal region image. The phase timing of the foveal region stream being sent over the transport layer is adjusted with respect to the background stream to correspond to the location of the foveal region within the overall image. This helps to reduce the amount of buffering needed at the receiver for blending the images together to create a final image to be driven to the display.

Abstract: A system-on-chip (SOC), includes a memory, a partition access module coupled to the memory, a partition requesting unit coupled to the partition access module, and a first input-output (IO) device coupled to the partition access module. The partition access module creates a first partition of the SOC. The first partition includes a first portion of a first processor, the first IO device, and a first portion of the memory. Based upon a partition request, the partition access module repartitions the SOC to create a dynamic partition. The dynamic partition includes the first portion of the first processor, the first input-output (IO) device, the first portion of the memory, and a second IO device not included in the first partition.

Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

Abstract: Disclosed herein is a region-based reference management system using in video frame encoding. Source content, such as video game streaming or remote desktop sharing, that includes scene changes or significant instantaneous changes in a region from one frame to the next can present encoding challenges. Techniques disclosed herein use hints about changes in regional frame content, dissect frame content into regions, and associate the dissected regions with stored reference frame data using the hints and information about the regions to more efficiently encode frames.

Abstract: A platform security processor is booted and reads a set of write-once memory bits to obtain a minimum security patch level (SPL). The security processor then verifies that a table SPL for a firmware security table is greater than or equal to the minimum SPL. The firmware security table includes a plurality of firmware identifiers for firmware code modules, and a plurality of check SPL values each associated with respective one of the firmware identifiers. The security processor verifies SPL values in a plurality of firmware code modules by, for each firmware code module, accessing the module to obtain its firmware SPL value and check if the respective firmware SPL value is equal to or greater than a respective check SPL value in the firmware security table.

Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.

Abstract: A Management Component Transport Protocol platform management subsystem includes an internal bridge, a first segment group, and a second segment group. The first segment group is coupled to the internal bridge. The second segment group is coupled to the internal bridge and the first segment group. The first segment group has a first plurality of Peripheral Component Interconnect Express (PCIe)-based buses. The second segment group has a second plurality of PCIe-based buses, wherein based on an identification (ID)-routed packet from the first segment group to the second segment group, the internal bridge routes the ID-routed packet to the second segment group.

Abstract: A method and processing device are disclosed for allocating hardware bandwidth capability for a virtual environment. The processing device comprises memory and a processor. The processor is configured to determine current hardware bandwidth usages for a plurality of virtual functions (VFs) executing on corresponding virtual machines (VMs), determine utilizations of hardware bandwidth capabilities of the VFs, reallocate the hardware bandwidth capabilities based on the determined utilizations and store the reallocated hardware bandwidth usages in a portion of the memory which is accessible to the VMs. Utilizations are determined, for example, based on current hardware bandwidth usages. The hardware bandwidth capabilities are, for example, reallocated by storing metadata indicating the hardware bandwidth capability allocated to each of the VFs.

Abstract: Some implementations provide systems, devices, and methods for implementing a cache replacement policy. A memory request is issued for attribute information associated with a node in an acceleration data structure. The attribute information associated with the node is inserted into a cache entry of the cache and an age associated with the cache entry is set to a value based on the attribute information, in response to the memory request causing a cache miss.

Abstract: A GPU is generally configured to detect changes in the rate of frame generation that can result from, for example, changes in the complexity of the frames being generated. In response to detecting the change in the rate of frame generation, the GPU identifies a corresponding change in the refresh rate that would be required to fully synchronize the refresh rate with the rate of frame generation. If the change in the refresh rate falls outside the boundaries of a specified or dynamically generated window, the GPU limits the change in refresh rate to the corresponding boundary.

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.