Patents Assigned to ATI Technologies
  • Patent number: 10250909
    Abstract: A processing device for use with a video conferencing network is provided. The processing device includes memory configured to store data and a processor. The processor is configured to determine a first sampling phase for a portion of first video data and chrominance sub-sample the portion of first video data using the first sampling phase. The processor is also configured to encode the sub-sampled portion of first video data and decode a sub-sampled, encoded portion of second video data. The processor is further configured to determine a second sampling phase at which the portion of second video data is chrominance sub-sampled and chrominance up-sample the portion of second video data using the second sample phase.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 2, 2019
    Assignee: ATI Technologies ULC
    Inventors: Boris Ivanovic, Allen J. Porter
  • Patent number: 10241925
    Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventors: Jimshed Mirza, Anthony Chan, Edwin Chi Yeung Pang
  • Patent number: 10242647
    Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventor: Yuxin Chen
  • Patent number: 10243727
    Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 26, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Winthrop Wu, James Goodman, Martin Kiernicki, Yoichi Shimokawa, William Thomas Morrison, Creighton Eldridge, David Kaplan
  • Patent number: 10230370
    Abstract: In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 12, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Mark Edward Frankovich
  • Patent number: 10223280
    Abstract: A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 5, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Vydhyanathan Kalyanasundharam, Yaniv Adiri, Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien
  • Patent number: 10218273
    Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Erhan Ergin, Dipanjan Sengupta, Elsie Lo, Stephen V. Kosonocky, Sree Rajesh Saha, Divya Guruja
  • Publication number: 20190056958
    Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Brian K. Bennett
  • Patent number: 10210845
    Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 19, 2019
    Assignee: ATI Technologies ULC
    Inventors: David I. J. Glen, Syed A. Hussain
  • Patent number: 10209991
    Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: February 19, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Meenakshi Sundaram Bhaskaran, Elliot H. Mednick, David A. Roberts, Anthony Asaro, Amin Farmahini-Farahani
  • Patent number: 10205956
    Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 12, 2019
    Assignee: ATI Technologies ULC
    Inventors: Konstantine Iourcha, Andrew S. C. Pomianowski
  • Patent number: 10198283
    Abstract: A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 5, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices (Shanghai) Co., LTD.
    Inventors: Jeffrey G. Cheng, Yinan Jiang, Guangwen Yang, Kelly Donald Clark Zytaruk, LingFei Liu, XiaoWei Wang
  • Patent number: 10198358
    Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 5, 2019
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Angel E. Socarras, Kostantinos Danny Christidis, Curtis Alan Gilgan, Alexander Fuad Ashkar
  • Patent number: 10198219
    Abstract: Described herein is a method and apparatus for en route translation of data by a data translation logic (DTL) on a solid state graphics (SSG) device as the data moves from a first memory architecture on the SSG device to a second memory architecture associated with a graphics processing units (GPU) on the SSG device or from the first memory architecture on the SSG device to a host memory in a host system that is connected to the SSG device.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 5, 2019
    Assignee: ATI Technologies ULC
    Inventor: Gabor Sines
  • Publication number: 20190028725
    Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 24, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Lei Zhang, Ji Zhou, Zhen Chen, Min Yu
  • Patent number: 10185386
    Abstract: A method and apparatus controls power consumption of a computing unit by determining a discrete frame buffer memory usage condition, such as when there is little real 3D activity (or other condition). When the discrete frame buffer memory usage condition is favorable for power savings, the method and apparatus reduces power to at least one bank of discrete frame buffer memory during runtime of an associated discrete graphics processor. The associated discrete graphics processor uses a portion of a system memory's frame buffer memory instead of the at least one bank of discrete frame buffer memory during runtime of the discrete graphics processor. When a user runs more intense 3D programs, the apparatus and method dynamically enables the discrete frame buffer or portion thereof such as one or more banks and reverts from using the system memory back to using the discrete frame buffer memory.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 22, 2019
    Assignee: ATI Technologies ULC
    Inventor: Wayne Chuck Louie
  • Patent number: 10185621
    Abstract: A video device having data lanes and a method of operating the video device includes obtaining a stream of debug data in response to a test operation, framing the stream of debug data independent of establishing a video blanking period, and transmitting the framed stream of debug data across one or more data lanes of the video link for operation between a video source device and a video sink device. The method also includes generating a stream of video data related to the test operation, framing the stream of video data to establish a video blanking period, and transmitting the framed stream of debug data concurrently with the framed stream of video data across the one or more data lanes of the video link.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 22, 2019
    Assignee: ATI Technologies ULD
    Inventor: Dennis Au
  • Publication number: 20190018699
    Abstract: A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 17, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Yinan Jiang, Andy Sung, Ahmed M. Abdelkhalek, Xiaowei Wang, Sidney D. Fortes
  • Patent number: 10181454
    Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: January 15, 2019
    Assignee: ATI Technologies ULC
    Inventor: Changyok Park
  • Patent number: 10176548
    Abstract: A processor includes a scheduler that governs which of a plurality of pending graphics contexts is selected for execution at a graphics pipeline of the processor. The processor also includes a plurality of flip queues storing data ready to be rendered at a display device. The executing graphics context can issue a flip request to change data at stored at one of the flip queues. In response to determining that the flip request targets a flip queue that is being used for rendering at the display device, the scheduler executes a context switch to schedule a different graphics context for execution at the graphics pipeline.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 8, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Gongxian Jeffrey Cheng