Patents Assigned to ATI Technologies
  • Publication number: 20180181340
    Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) or a discrete GPU (dGPU). In particular, a method is described for transferring data between the first memory architecture and the second memory architecture that bypasses interaction with a system memory of a processor and a root complex. A transfer command is sent from the processor, (or a host agent in the GPU or dGPU), to a first memory architecture controller. The first memory architecture controller initiates the transfer of the data directly between the first memory architecture and the second memory architecture. The method bypasses: 1) a host root complex; and 2) storing the data in the system memory and then having to transfer the data to the second memory architecture or the first memory architecture.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Applicant: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Publication number: 20180181519
    Abstract: Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable memory. A front end processor connected to a Peripheral Component Interconnect Express (PCIe) switch performs as a front end interface to the block addressable I/O device to emulate byte addressability. A PCIe device, such as a graphics processing unit (GPU), can directly access the necessary bytes via the front end processor from the block addressable I/O device. The PCIe compatible devices can access data from the block I/O devices without having to go through system memory and a host processor. In an implementation, a system can include block addressable I/O, byte addressable I/O and hybrids thereof which support direct access to byte addressable memory by the host processor, GPU and any other PCIe compatible device.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Applicant: ATI Technologies ULC
    Inventor: Gongxian Jeffrey Cheng
  • Publication number: 20180181488
    Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Mark Fowler, Jimshed Mirza, Anthony Asaro
  • Publication number: 20180181520
    Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.
    Type: Application
    Filed: April 28, 2017
    Publication date: June 28, 2018
    Applicant: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Patent number: 10002028
    Abstract: A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 19, 2018
    Assignee: ATI Technologies ULC
    Inventors: Joseph Andonieh, Arshad Rahman
  • Publication number: 20180165872
    Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
  • Patent number: 9984664
    Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 29, 2018
    Assignee: ATI Technologies ULC
    Inventors: David I. J. Glen, Syed A. Hussain
  • Publication number: 20180143680
    Abstract: A processing apparatus is provided which includes memory configured to store hardware parameter settings for each of a plurality of applications. The processing apparatus also includes a processor in communication with the memory configured to store, in the memory, the hardware parameter settings, identify one of the plurality of applications as a currently executing application and control an operation of hardware by tuning a plurality of hardware parameters according to the stored hardware parameter settings for the identified application.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Applicant: ATI Technologies ULC
    Inventors: Shahriar Pezeshgi, Jun Huang, Mohammad Hamed Mousazadeh, Alexander S. Duenas
  • Patent number: 9977854
    Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 22, 2018
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Omid Rowhani, Ioan Cordos, Kerry Hamel, Donald Clay
  • Patent number: 9972275
    Abstract: The present disclosure relates to a method and system for content presentation in a main processor shutoff mode. A method for content presentation includes transferring content to at least one of a co-processor and storage accessible by the co-processor and shutting off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. The content may include at least one of multimedia data, text data, and image data. A disclosed system includes a main processor in communication with a co-processor. The main processor includes data transfer logic operative to transfer the content and to shut off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: May 15, 2018
    Assignee: ATI Technologies ULC
    Inventor: Bin Xie
  • Patent number: 9965392
    Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 9959593
    Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 1, 2018
    Assignee: ATI Technologies ULC
    Inventors: Milivoje Aleksic, Raymond M. Li, Danny H. M. Cheng, Carl K. Mizuyabu, Anthony Asaro
  • Publication number: 20180109804
    Abstract: The present disclosure is directed to techniques for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Applicant: ATI Technologies ULC
    Inventor: Mehdi Saeedi
  • Patent number: 9947114
    Abstract: An apparatus and methods for modifying gradation in an image frame determine a blend factor indicating a first weighting associated with a previously processed portion of the image frame. The apparatus and methods generate a weighted value associated with a current region of the image frame based on the current region of the image frame and based on applying the first weighting to the previously processed portion of the image frame so as to modify the gradation in the image frame.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 17, 2018
    Assignee: ATI Technologies ULC
    Inventors: Boris Ivanovic, Tiberiu Visan
  • Publication number: 20180082399
    Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.
    Type: Application
    Filed: January 25, 2017
    Publication date: March 22, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre
  • Publication number: 20180084270
    Abstract: A processing apparatus is provided that includes an encoder configured to encode current frames of video data using previously encoded reference frames and perform motion searches within a search window about each of a plurality of co-located portions of a reference frame. The processing apparatus also includes a processor configured to determine, prior to performing the motion searches, which locations of the reference frame to reload the search window according to a threshold number of search window reloads using predicted motions of portions of the reference frame corresponding to each of the locations. The processor is also configured to cause the encoder to reload the search window at the determined locations of the reference frame and, for each of the remaining locations of the reference frame, slide the search window in a first direction indicated by the location of the next co-located portion of the reference frame.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 22, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ihab Amer, Gabor Sines, Edward Harold, Jinbo Qiu, Lei Zhang, Yang Liu, Zhen Chen, Ying Luo, Shu-Hsien Wu, Zhong Cai
  • Patent number: 9922395
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 20, 2018
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Patent number: 9924134
    Abstract: An image rendering unit (IRU) of a device determines the dynamic frame rate capabilities (DFRCs) of a display and an image frame rate of content to be displayed. Preferably, the DFRCs are stored in a storage device deployed within the display itself. Based on the DFRCs and the image frame rate for the content, the IRU determines an updated frame rate and thereafter provides the content to the display at the updated frame rate. Where control of power consumption is desired, selection of a reduced frame rate can effect a power savings. In this manner, the present invention provides flexible control over display frame rates and/or power consumption of the device.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 20, 2018
    Assignee: ATI Technologies ULC
    Inventor: David I. J. Glen
  • Patent number: 9910788
    Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: March 6, 2018
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Philip J. Rogers, Benjamin T. Sander, Anthony Asaro
  • Patent number: 9911397
    Abstract: Briefly, methods and apparatus to provide image content to, and display image content on, variable refresh rate displays with reduced input lag. The methods and apparatus allow for image tearing, or the displaying of image content from more than one video frame, when the render rate of a provided video frame falls outside the display refresh rate range of a variable refresh rate display when the display is refreshing with a previous frame (e.g. the display is in active refresh), thus reducing the input lag of the content of the provided video frame. The methods and apparatus may also prevent image tearing when the render rate of provided video frames is within the display refresh rate range of a display.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: March 6, 2018
    Assignee: ATI Technologies ULC
    Inventor: David Glen