Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.

Abstract: A method, an apparatus, and a non-transitory computer readable medium for performing 2D to 3D conversion are presented. A 2D input source is extracted into left and right 3D images. Motion vectors are calculated for the left and right 3D images. Frame rate conversion is performed on the left 3D image and the right 3D image, using the respective calculated motion vectors, to produce motion compensated left and right 3D images. The left and right 3D images and the motion compensated left and right 3D images are reordered for display.

Abstract: A method and apparatus of dejuddering image data includes receiving a video data signal that includes a plurality of successive source frames. A first source frame of the plurality of successive source frames is displayed a predetermined number of times. A first black frame is displayed, and successive source frames are displayed.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract: Tessellation triangles, which are used to model three-dimensional surfaces in computer-generated graphics, can be more efficiently calculated by retrieving tessellation triangle vertices and Bezier-function coefficients using a single, two-part address.

Abstract: At one of a video source device and a video sink device, an indication of video processing capabilities of the other of the video source device and said video sink device is received. Based upon the indication and an indication of video processing capabilities of the one device, one of a plurality of video processing algorithms is selected for execution by the one device. The selecting may be based upon a set of precedence rules. Categories of video processing may for example include scan-rate conversion, interlacing, de-interlacing, de-noise, scaling, color correction, contrast correction and detail enhancement.

Abstract: A video source, a display and a method of processing multilayered video are disclosed. The video source decodes a multilayered video bit stream to transmit synchronized streams of decompressed video images and corresponding overlay images to an interconnected display. The display receives separate streams of video and overlay images. Transmission and reception of corresponding video and overlay images is synchronized in time. A video image received in the display can be selectively processed separately from its corresponding overlay image. The video image as processed at the display is later composited with its corresponding overlay image to form an output image for display.

Abstract: A method and apparatus provides for controlling the distribution and installation of operating systems. In one example, the method and apparatus partitions a storage device of a device into a first partition and a second partition. The method and apparatus installs a first operating system into the first partition of the storage device, obtains an image of the second operating system, the image including at least the second operating system pre-configured for operation with the device, and installs, using the first operating system, the image of the operating system to the second partition of the storage device. In an embodiment, the image is transmitted from one or more other devices. In an embodiment, two or more images are cached on the device according to the likelihood they will be used in the future.

Abstract: Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.

Abstract: A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.

Abstract: An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.

Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.

Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.

Abstract: The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.

Abstract: The present disclosure relates to a method and system for providing an image for display on a monitor. A method for providing an image for display includes detecting an exclusive display mode. In the exclusive display mode, an application is blocked from display on a monitor. In response to detecting the exclusive display mode, a composited surface is generated that comprises display data of a blocked application surface and display data of an exclusive application surface. A disclosed system includes a display mode detector that detects an exclusive display mode and a surface compositing module that causes a generation of a composited surface.

Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.

Abstract: Provided is a method and system for preloading a cache on a graphical processing unit. The method includes receiving a command message, the command message including data related to a portion of memory. The method also includes interpreting the command message, identifying policy information of the cache, identifying a location and size of the portion of memory, and creating a fetch message including data related to contents of the portion, wherein the fetch message causes the cache to preload data of the portion of memory.

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

Abstract: In an embodiment, a graphics processing device is provided. The graphics processing device includes a global clock generator configured to generate a global clock signal and a plurality of graphics pipelines each configured to transmit image frames to a respective display device. Each of the graphics pipelines comprises a timing generator. Each of the timing generators is configured to generate a respective virtual clock signal based on the global clock signal and wherein each virtual clock signal is used to advance logic of a respective one of the display devices.