Patents Assigned to ATI Technologies
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Patent number: 8400457Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.Type: GrantFiled: December 9, 2009Date of Patent: March 19, 2013Assignee: ATI Technologies, Inc.Inventors: Jonathan L. Campbell, Maurice Ribble
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Patent number: 8401371Abstract: A content player includes a pausable mass storage device player that can be used to record and play content. The pausable mass storage device can become paused in response to an assertion of a pause signal. Once paused, the content player remains paused until the pause signal is deasserted. The content player also includes an event detector that is coupled to the pausable mass storage device player. The content player detects a non-viewer initiated event, (e.g., an automatic event such as the receipt of an email with embedded enhanced content), and to assert the pause signal in response thereto. The content player receives content, detects an event, and in response to detecting the event, pauses the content to a presentation device; and spools the content onto the mass storage device.Type: GrantFiled: August 24, 2000Date of Patent: March 19, 2013Assignee: ATI Technologies ULCInventors: Stephen J. Orr, Godfrey W. Cheng
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Patent number: 8396129Abstract: A mipmap generator generates pairs of mipmaps that are each of a lower resolution that its respective source image. A single-pass, gradient-based motion vector generator generates an image motion vector map having values that represent the motion trajectories for pixels in the first and second source images. An image interpolator generates an interpolated image based on the source images and the image motion vector map. A motion detector generates a motion factor map based on a pair of mipmaps from those generated by the mipmap generator that represents a detected degree of motion between the first and second source images. The blending module generates a blended, upconverted new image using the motion factor map, the interpolated image and one of the first and second motion maps.Type: GrantFiled: December 28, 2007Date of Patent: March 12, 2013Assignee: ATI Technologies ULCInventor: Jeff X. Wei
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Patent number: 8397079Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.Type: GrantFiled: June 4, 2008Date of Patent: March 12, 2013Assignee: ATI Technologies ULCInventors: Serag M. GadelRab, Bin Du, Zeeshan S. Syed, Denis Foley
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Patent number: 8395709Abstract: A method and apparatus for reducing motion judder in a 3D input source are disclosed. The 3D input source is separated into left and right images. Motion vectors for the left and right images are calculated. Frame rate conversion is performed on the left and right images, to produce motion compensated left and right images. The left and right images and the motion compensated left and right images are reordered for display. Alternatively, the motion estimation and motion compensation can be performed on the 3D input source, and the input image and the motion compensated image can then be separated into respective left and right images. The method and apparatus can be adapted to perform 2D to 3D conversion by extracting a 2D input source into left and right 3D images and performing motion estimation and motion compensation.Type: GrantFiled: March 4, 2009Date of Patent: March 12, 2013Assignees: ATI Technology ULC, Advanced Micro Devices, Inc.Inventors: Sunkwang Hong, Samir N. Hulyalkar
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Patent number: 8394672Abstract: A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.Type: GrantFiled: August 14, 2010Date of Patent: March 12, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
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Publication number: 20130060505Abstract: Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: ATI Technologies ULC.Inventor: Michael J. Brennan
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Patent number: 8390687Abstract: A method of automated video device testing, and source and sink video devices are disclosed. A test signal may be provided by way of a video link from a video source to a video sink, over a video link extending therebetween. The method includes receiving on the video link a request from the video sink to provide the test signal; identifying based on the request, a requested test signal; providing the requested test signal from the video source to the video sink over the video link. In another embodiment, a video sink may be queried over a video link to determine a metric describing at least a portion of know video signal, as received and determined at the video sink to verify integrity of the video signal at the video sink.Type: GrantFiled: March 18, 2008Date of Patent: March 5, 2013Assignee: ATI Technologies ULCInventors: David Glen, Betty Luk
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Patent number: 8389340Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.Type: GrantFiled: September 28, 2011Date of Patent: March 5, 2013Assignee: ATI Technologies ULCInventors: Roden R. Topacio, Neil McLellan
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Publication number: 20130050448Abstract: Circuitry for better integrating multiview-based 3D display technology with the human visual system includes logic that identifies an object of interest from a plurality of objects in a multiview-based 3D scene displayed on one or more displays and provides focus adjustment control data for eyewear to view the 3D scene based on perceived distance data corresponding to the identified at least one object of interest and the identified at least one object of interest. In one example, the circuitry includes logic that determines the perceived distance data corresponding to the at least one object of interest based on inter-object distance data indicating a horizontal offset between the at least one object of interest in a first scene view and the same at least one object of interest in a second scene view and display distance data indicating the distance between one or more display screens and a viewing position. Related methods are also set forth.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: ATI Technologies ULCInventor: Philip L. Swan
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Publication number: 20130050414Abstract: A method and system are provided for navigating and selecting objects within a 3D video image by computing a depth coordinate based upon two-dimensional (2D) image information from left and right views of such objects. In accordance with preferred embodiments, commonly available computer navigation devices and input devices can be used to achieve such navigation and object selection.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: ATI Technologies ULCInventors: Pavel Siniavine, Jitesh Arora, Alexander Zorin, Gabor Sines, Xingping Cao, Philip L. Swan, Mohamed K. Cherif, Edward Callway
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Patent number: 8386687Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.Type: GrantFiled: February 17, 2012Date of Patent: February 26, 2013Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Robert W. Bloemer
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Patent number: 8384424Abstract: An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.Type: GrantFiled: April 8, 2011Date of Patent: February 26, 2013Assignee: ATI Technologies ULCInventor: Junho J. H. Cho
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Patent number: 8384479Abstract: An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node.Type: GrantFiled: March 8, 2010Date of Patent: February 26, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Saeed Abbasi, Nima Gilanpour, Vincent Law
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Patent number: 8378471Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.Type: GrantFiled: January 22, 2010Date of Patent: February 19, 2013Assignee: ATI Technologies ULCInventors: Roden R. Topacio, Vincent Chan, Fan Yeung
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Patent number: 8373709Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.Type: GrantFiled: December 19, 2008Date of Patent: February 12, 2013Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Shahin Solki, Stephen Morein, Mark S. Grossman
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Publication number: 20130009970Abstract: Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: ATI Technologies ULCInventor: Collis Quinn Troy Carter
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Patent number: 8350867Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.Type: GrantFiled: December 22, 2009Date of Patent: January 8, 2013Assignee: ATI Technologies ULCInventors: Raymond F. Dumbeck, Andrew W. Dodd, Michael Casey Gotcher
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Patent number: 8345756Abstract: Embodiments of a method and system for intra-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an intra-prediction operation. In an embodiment, intra-prediction is performed on a frame basis such that intra-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the intra-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.Type: GrantFiled: August 31, 2006Date of Patent: January 1, 2013Assignee: ATI Technologies, Inc.Inventors: Alexander Lyashevsky, Jason Yang, Arcot J. Preetham
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Patent number: 8344505Abstract: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.Type: GrantFiled: August 29, 2007Date of Patent: January 1, 2013Assignee: ATI Technologies ULCInventors: Neil Mclellan, Adam Zbrzezny