Abstract: A method includes determining white balance calibration color ratios for a plurality of illumination sources by using a representative camera of a given type to establish a set of ratios. Because the ratios are fixed for the given camera type, a plurality of cameras of the type may store the fixed ratios, and calibrate by measuring only the reference illumination source. Later white balancing is achieved by using the measured reference illumination source color ratios and the stored fixed ratios as scaling factors to map from the reference illumination source to any other illumination source. The method includes an off-line advance calibration procedure to obtain the fixed ratios, an on-line per camera calibration procedure to obtain color ratios for the reference source, and subsequent white balancing which uses the fixed ratios/scaling factors and the reference source color ratios.

Abstract: A circuit includes an enhanced frequency range linear pulse code modulation conversion circuit. The enhanced frequency range linear pulse code modulation conversion circuit is driven by a clock signal within a frequency range. The enhanced frequency range linear pulse code modulation conversion circuit provides enhanced frequency range linear pulse code modulated information. More specifically, the enhanced frequency range linear pulse code modulation conversion circuit is provided by selectively decimating and interpolating non-enhanced frequency range linear pulse code modulated information based on a desired output sampling frequency and the frequency range.

Abstract: A method and apparatus for correcting a rotation of a video frame are described. According to a method, an amount of the rotation of the video frame with respect to a reference is determined. The rotation of the video frame is corrected based at least in part on the detected amount of the rotation of the video frame.

Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor structure. A first via is formed in the first interconnect layer and in electrical contact with the first conductor structure. The first via has a first oval footprint.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: Circuitry, apparatus and methods provide flicker detection and improved image generation for digital cameras that employ image sensors. In one example, circuitry and methods are operative to compare a first captured frame with a second captured frame that may be, for example, sequential and consecutive or non-consecutive if desired, to determine misalignment of scene content between the frames. A realigned second frame is produced by realigning the second frame with the first frame if the frames are determined to be misaligned. Luminance data from the realigned second frame and luminance data from the pixels of the first frame are used to determine if an undesired flicker condition exists. If an undesired flicker condition is detected, exposure time control information is generated for output to the imaging sensor that captured the frame, to reduce flicker. This operation may be done, for example, during a preview mode for a digital camera, or may be performed at any other suitable time.

Abstract: One of a video source device and a video sink device may: (a) deactivate a video processing function at the one device and send a command for causing the other of the video source device and the video sink device to activate the video processing function; (b) activate the video processing function at the one device and send a command for causing the other device to deactivate the video processing function; and (c) based on user input indicating whether (a) or (b) resulted in a preferred video image, effect (a) or (b). The one device may receive an indication of video processing functions of which the other device is capable, such that (a), (b) and (c) may be performed for each indicated video processing function of which the one device is also capable. A user interface including at least one selectable control for indicating whether a video image resulting from (a) or (b) is preferred may be displayed.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Abstract: An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions.

Abstract: A method and apparatus for enhancing an input image to produce a contrast enhanced output image is disclosed. The method involves producing a contrast value for each pixel in the input image, the contrast value being proportional to an intensity gradient between each respective pixel and at least one pixel adjacent the respective pixel. The method also involves selecting pixels in the input image having respective contrast values that meet a first criterion, thereby forming a selected plurality of pixels and producing a frequency distribution of intensity values of the selected plurality of pixels. The method further involves selecting at least one range of intensity values in the frequency distribution that meet a second criterion, thereby producing a selected range of intensity values for enhancement.

Abstract: A video processing device comprises a display interface coupleable to a display device and a display controller configured to transmit a video signal via an output node of the display interface. The video signal comprises an active segment comprising video information and an inactive segment comprising synchronization information. The video processing device further comprises a display detector configured to determine whether the display device is coupled to the display interface based on a comparison of a first voltage at the output node during transmission of the inactive segment to a second voltage.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit.

Abstract: An embedded, programmable motion blur system and method is described herein. Embodiments include applying displacement on a vertex level and amplification on a primitive level within a graphics pipeline. Embodiments include receiving a plurality of vertices in a first component of a graphics processing unit (GPU), displacing each of the plurality of vertices, receiving a primitive that includes at least one of the displaced vertices in a second component of the GPU, and transforming the primitive. In one embodiment, transforming comprises at least one of translation, scaling, and rotation. Further included are generating a plurality of primitive samples over a time aperture, and outputting the plurality of primitive samples to further components of the GPU for further processing for display of the scene with motion blur.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A method and apparatus for protecting access to audio and/or video data is accomplished when data is received, where the data may be audio data and/or video data. Having received the data, it is interpreted to determine whether an embedded data access parameter is active. If so, an indication of the particular type of data access is generated. The data access parameter may control access to the data as at least one of: copy restrictions, viewing restrictions, and/or use restrictions. The indication is subsequently provided to a computer system such that unauthorized accessing, including unauthorized copying, of the video and/or audio data is prohibited.