Abstract: A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.

Abstract: An apparatus and method for facilitating program changes. The apparatus and method include a controller for detecting a change program request and for outputting change event data when a change event is detected. A non-active video information replacement module is coupled to the controller for receiving non-active video information and the change event data. When the replacement module receives change event data, a clear code generator generates clear code data that replaces non-active video information, and the non-active video information replacement module generates modified non-active video information. The modified non-active video information is provided to an output stage, whereupon the clear code data resets a non-active video information field within a display device, thereby preventing the display of erroneous information by a display within the output stage. Thereupon, clear code data is synthetically inserted within non-active video information upon the occurrence of a change event.

Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.

Abstract: A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The method and apparatus further includes a comparator coupled to receive an input strength indicator signal from the receiver and operative to generate a comparative strength signal based on the comparison of the input signal strength indicator signal and a reference strength signal. Furthermore, the method and apparatus includes a tuner coupled to the clock counter so the tuner receives the time value from the counter, and coupled to the comparator to receive the comparative strength signal from the comparator, whereupon the tuner then generates a tuning signal utilized for an iterative tuning process to fine tune a memory interface.

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.

Abstract: A method and apparatus utilizes a three dimensional rendering engine to rotate an image based on user selected or otherwise determined screen orientation. A vertex coordinate transformation is defined for a rotated destination image. The source image is used as a texture for texture mapping during rendering operation to produce rotated image. In one embodiment, a separate set of software instructions is used for each orientation mode. Accordingly, a non-pixel by pixel based 3D rotation may be carried out using a 3D rendering engine to avoid a single parameter based seriatim pixel by pixel based orientation.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In an embodiment, the vapor configuration is modified to include fins that define a cross-flow heat exchanger there the vapor from the vapor chamber serves as the fluid in the vertical cross-flow in the heat exchanger and natural or forced cooling air serves as the horizontal cross-flow for the heat exchanger.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In a proposed embodiment, at least one heat pipe is used to transfer heat from the condensation portion of a vapor chamber to cool a bottom portion of a finned heat dissipation space and transfer the heat to a colder location on the heat fins. In another proposed embodiment, the water vapor chamber is placed in a heat sink and is adapted to thermally connect to at least one heat pipe.

Abstract: Described are methods, devices, and systems for optimizing presentation of an image-bearing signal on a display device equipped with at least one adjustable picture control variable. The methods utilize, and the devices include, a picture control setting generator for determining different picture control settings, and an on-screen display generator for producing an on-screen display including multiple image cells (e.g., a mosaic). Each cell displays the same received image-bearing signal tuned according to a respective one of the different picture control settings. An end user selects among the different cells, choosing a cell that provides a preferred picture quality. In some embodiments, the picture control setting generator determines new picture control settings in response to the selected cell.

Abstract: A de-interlacer includes recursive motion history map generating circuitry operative to determine a motion value associated with one or more pixels in interlaced fields based on pixel intensity information from at least two neighboring same polarity fields. The recursive motion history map generating circuitry generates a motion history map containing recursively generated motion history values for use in de-interlacing interlaced fields wherein the recursively generated motion history values are based, at least in part, on a decay function.

Abstract: A demodulated multimedia signal is generated based on a captured handheld multimedia signal or a captured terrestrial multimedia signal where the handheld multimedia signal is formatted for reproduction on a handheld device and the terrestrial multimedia signal is formatted for reproduction on a computer system. The demodulated multimedia signal or a decoded multimedia signal (based on the demodulated multimedia signal) is transferred to a computer system for visual and/or audible reproduction on a computer system or for transmission to another computer system. The video information associated with the transferred signal is scaled by the computer system prior to display to match the display characteristics and capabilities of the computer system. The transferred signal may correspond to multiple channels of multimedia signals thereby enabling the display of multiple multimedia signals at the same time.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A tool changer comprising a master module and a tool module includes a rapid-connect communication bus between the master and tool modules. A unique tool identification number, along with other tool-related information, may be transmitted from the tool module to the master module within about 250 msec of the master and tool modules coupling together. The master module includes a robotic system communications network node connected to the rapid-connect communication bus, and operative to transmit data between the tool and the network via the communication bus. The need for a separate network node in the tool module is obviated, reducing cost and reducing the start-up time required to initialize such a network node upon connecting to a new tool. The rapid-connect communication bus may be a serial bus.

Abstract: The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.

Abstract: In a method and apparatus for generating a power supply voltage, an integrated circuit including an adaptive power supply voltage circuit is provided where a target signal is generated representing an ideal or approximated ideal performance characteristic of a functional block operating with the power supply voltage. A generated functional block test signal is generated representing the performance characteristic of the functional block under these conditions. The adaptive power supply voltage circuit compares the target signal with the generated functional block test signal and adjusts the power supply voltage continuously until the target signal and generated functional block test signal are substantially equal. When the target signal and generated functional block test signal are substantially equal, the power supply voltage is locked for subsequent use. By optimizing the power supply voltage, minimal power dissipation is provided.

Abstract: A method and apparatus for automated testing of display signals from video graphics circuitry includes capturing display signals that are provided from a processing device to the display device. The method and apparatus further includes converting the display signals into data acquisition signals, where a data acquisition signal includes a converted display signal having the display information contained therein wherein the data acquisition signal is in a form capable of being directly analyzed by a testing system. Furthermore, the method and apparatus includes providing the data acquisition signals to a test system that tests the display signals.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: Command handling logic receives a plurality of command requests and groups the plurality of command requests into one of a plurality of command tracking classifications to produce classification tagged command requests. The plurality of classification tagged command requests and corresponding plurality of command responses are communicated via a bus. Command classification tracking logic tracks the plurality of classification tagged command requests and a corresponding plurality of classification tagged command response to determine when there are no outstanding command requests associated with one of the plurality of command tracking classifications. There are no outstanding command requests associated with one of the plurality of command tracking classifications when the command classification tracking logic has received a number of classification tagged command responses equal to the number of sent classification tagged command requests associated with the same command tracking classification.

Abstract: A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.