Patents Assigned to ATI
  • Patent number: 6744432
    Abstract: A method and apparatus for determining a rear most Z value for a pixel block is presented, where the pixel block is a portion of the image data for a frame as stored in a frame buffer. The frame buffer is stored in a DRAM memory structure that is included on an integrated circuit along with a render backend block that blends received fragments from a three-dimensional (3D) video graphics pipeline with the image data stored in the frame buffer. The 3D video graphics pipeline is located on a video graphics processing integrated circuit separate from the integrated circuit storing the frame buffer and render backend block. The integrated circuit storing the frame buffer includes a value determination block that determines the rear most Z value. The value determination block includes a data serialization block that serializes the bits corresponding to the Z values for the pixels included in the pixel block to produce a plurality of corresponding serial bit streams.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: June 1, 2004
    Assignee: ATI International Srl
    Inventor: Stephen L. Morein
  • Patent number: 6745308
    Abstract: A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: June 1, 2004
    Assignee: ATI Technologies, Inc.
    Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura
  • Patent number: 6738058
    Abstract: A method and apparatus for compression and decompression of a two dimensional video object such that the video object may subsequently be displayed as a three dimensional object is generally accomplished by a set-up engine which receives vertex parameters and generates a plurality of derivatives and Bresenham parameters, therefrom. The derivatives and Bresenham parameters are provided to an edgewalker circuit which produces, therefrom, a plurality of spans which, in turn, is converted in to a set of texel addresses by a texel address generator. A texel fetch circuit receives the set of texel addresses and uses the addresses to retrieve a set of texels, which is subsequently processed by a texel processor to produce a filtered pixel. To retrieve the set of texels, the texel fetch circuit retrieves a set of indexes based on the texel addresses and uses the set of texels to retrieve the set of texels from a codebook.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: May 18, 2004
    Assignee: ATI Technologies, Inc.
    Inventors: Andrew E. Gruber, Mark A. Sprague
  • Patent number: 6737030
    Abstract: A method is provided to optimize separation of zirconium from hafnium by extraction of a feed mix including (Zr+Hf)OCl2 with a thiocyanate-containing organic phase. The method includes maintaining the TA/MO2 ratio in a range from greater than about 2.55 to about 3.5.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: May 18, 2004
    Assignee: ATI Properties, Inc.
    Inventors: James A. Sommers, Jeff G. Perrine
  • Patent number: 6730264
    Abstract: A nickel-base alloy includes, in weight percent, up to about 0.10 percent carbon; about 12 up to about 20 percent chromium; up to about 4 percent molybdenum; up to about 6 percent tungsten, wherein the sum of molybdenum and tungsten is at least about 2 percent and not more than about 8 percent; about 5 up to about 12 percent cobalt; up to about 14 percent iron; about 4 percent up to about 8 percent niobium; about 0.6 percent up to about 2.6 percent aluminum; about 0.4 percent up to about 1.4 percent titanium; about 0.003 percent up to about 0.03 percent phosphorous; about 0.003 percent up to about 0.015 percent boron; nickel; and incidental impurities. The sum of atomic percent aluminum and atomic percent titanium is from about 2 to about 6 percent, the ratio of atomic percent aluminum to atomic percent titanium is at least about 1.5, and the atomic percent of aluminum plus titanium divided by the atomic percent of niobium equals about 0.8 to about 1.3.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 4, 2004
    Assignee: ATI Properties, Inc.
    Inventor: Wei-Di Cao
  • Patent number: 6731294
    Abstract: A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: May 4, 2004
    Assignee: ATI International SRL
    Inventors: Michael Andrew Mang, Michael Mantor
  • Patent number: 6728869
    Abstract: A method and apparatus for avoiding latency in a processing system that includes a memory for storing intermediate results is presented. The processing system stores results produced by an operation unit in memory, where the results may be used by subsequent dependent operations. In order to avoid the latency of the memory, the output for the operation unit may be routed directly back into the operation unit as a subsequent operand. Furthermore, one or more memory bypass registers are included such that the results produced by the operation unit during recent operations that have not yet satisfied the latency requirements of the memory are also available. A first memory bypass register may thus provide the result of an operation that completed one cycle earlier, a second memory bypass register may provide the result of an operation that completed two cycles earlier, etc.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: April 27, 2004
    Assignee: ATI International Srl
    Inventors: Michael Andrew Mang, Michael Mantor, Robert Scott Hartog
  • Patent number: 6728584
    Abstract: The invention synchronizes and mixes multiple streams at different sampling rates by selectively accessing portions of the received streams in a sequence that allows for independent input and output frame rates. The sequence that is used to access the received streams is irregular with regard to the output frames, and formulated such that the input and output frames are synchronized to a super-frame that corresponds to a least common multiple frame in a conventional synchronizing and mixing system.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: April 27, 2004
    Assignee: ATI Technologies
    Inventors: Tieying Duan, Vladimir F. Giemborek, John S. Kitamura
  • Patent number: 6728820
    Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: April 27, 2004
    Assignee: ATI International SRL
    Inventors: Lee Brian, Indra Laksono, Antonio Asaro, Andrew E. Gruber, Gordon Caruk, Milivoje Aleksic
  • Patent number: 6720964
    Abstract: A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 13, 2004
    Assignee: ATI International SRL
    Inventors: Mark C. Fowler, Stephen Morein, Andi Skende, Kevin M. Olson
  • Patent number: 6719858
    Abstract: A method of producing a nickel base alloy includes casting the alloy within a casting mold and subsequently annealing and overaging the ingot at at least 1200° F. (649° C.) for at least 10 hours. The ingot is electroslag remelted at a melt rate of at least 8 lbs/min. (3.63 kg/min.), and the ESR ingot is then transferred to a heating furnace within 4 hours of complete solidification and is subjected to a novel post-ESR heat treatment. A suitable VAR electrode is provided form the ESR ingot, and the electrode is vacuum arc remelted at a melt rate of 8 to 11 lbs/minute (3.63 to 5.00 kg/minute) to provide a VAR ingot. The method allows premium quality VAR ingots having diameters greater than 30 inches (762 mm) to be prepared from Alloy 718 and other nickel base superalloys subject to significant segregation on casting.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: April 13, 2004
    Assignee: ATI Properties, Inc.
    Inventors: Betsy J. Bond, Laurence A. Jackman, A. Stewart Ballantyne
  • Patent number: 6717620
    Abstract: A method and apparatus for decompressing compressed data, which includes video data that has been compressed in accordance with the MPEG 2 standard, wherein the processing begins by retrieving components from a non-local memory at a rate that is independent of the rate in which the components were written into the non-local memory. The components include motion vectors and run/level data. As the components are retrieved from memory, the run/level data is used to produce representations of the uncompressed data. As the representations of the uncompressed data are generated, they are processed based on the motion vector data to recapture the uncompressed data. The uncompressed data is then stored in a frame buffer for subsequent display.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 6, 2004
    Assignee: ATI Technologies, Inc.
    Inventors: Paul Chow, Allen J. Porter, David A. Strasser, Antonio Asaro, Indra Laksono, Biljana D. Simsic
  • Patent number: 6717987
    Abstract: A method and apparatus compresses digital information based on an interpolation function such as used by a graphic engine scaler. Luma error information is determined based on the interpolation function and original luma data. A luma error quantizer quantizes the luma error information to determine a quantized error value on a per pixel basis. The quantized luma error value is compressed as part of compressed video information. In addition, chroma information is also compressed and combined with the compressed luma and compressed error information. The video compression method and apparatus stores compressed digital luma information, compressed digital chroma information, and compressed quantized error information (values) as the compressed video information on a per frame basis.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: April 6, 2004
    Assignee: ATI International SRL
    Inventors: Anthony D. Scarpino, Arshad S. Rahman
  • Patent number: 6717989
    Abstract: The video decoding apparatus and method includes providing a storage pointer command over a bus for a video decoder, wherein the storage pointer command contains index data associated with compressed video data. The index data represents, for example, a buffer storage location in a buffer that stores both decoded video being displayed and simultaneously uses another portion of the same buffer for decoding, such that the index data represents the storage location where corresponding decoded data is finally stored before display. The index data is compared with a current index or pointer associated with a current display line of a display engine. The apparatus and method includes stalling storage of compressed or uncompressed video data based on the comparison.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: April 6, 2004
    Assignee: ATI International Srl
    Inventors: Biljana D. Simsic, Michael Frank
  • Patent number: 6715053
    Abstract: An address access control system dynamically forms a plurality of address ranges in a predefined unified address structure during operation of a computer system. A plurality of memory clients is operatively connected to the unified address structure. A plurality of capabilities is also provided with respect to memory clients accessing address ranges. A memory controller is operatively connected to the plurality of memory clients and to the unified address structure. The memory controller dynamically structures an association of a respective range of the plurality of ranges with at least one respective capability of a plurality of capabilities for at least one memory client of the plurality of memory clients.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: March 30, 2004
    Assignee: ATI International SRL
    Inventor: Gordon F. Grigor
  • Patent number: 6714720
    Abstract: A method and apparatus for storing multimedia data for use in a digital VCR includes processing that begins by maintaining a first link list of a plurality of memory sections, where the first link list links the plurality of memory sections as a circular buffer. The processing then continues by receiving a stream of multimedia data. The processing then continues by storing the stream of multimedia data in at least some of the memory sections of the plurality of memory sections. The processing then continues by receiving a request for independent storage of a selected portion of the stream of multimedia data, e.g., the user desires to have a permanent copy of a particular program. The processing further continues by generating a second link list for a set of memory sections of the at least some of the memory sections. The set of memory sections stores the selected portion of the stream of multimedia data.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: March 30, 2004
    Assignee: ATI International Srl
    Inventors: Michael Lightstone, Stefan Eckart, Richard Webb, Haitao Guo, Xiaohua Yang, Fabio Ingrao
  • Patent number: 6715089
    Abstract: A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: March 30, 2004
    Assignee: ATI International SRL
    Inventor: Andrej Zdravkovic
  • Publication number: 20040057535
    Abstract: A robust data extension added to a standard 8VSB digital television signal is used to improve the performance of a digital television receiver. The robust data extension is added to a standard 8VSB digital television transmission system by encoding high priority data packets in a rate ½ trellis encoder. The high priority data ½ trellis encoded packets are then multiplexed with normal data packets and input into the normal data service of an 8VSB system, which further contains a rate ⅔ trellis encoder. The combined trellis encoding results in a rate ⅓ trellis encoding for robust data packets and a rate ⅔ trellis encoding for normal packets. Backward compatibility with existing receivers is maintained for 1) 8VSB signaling, 2) trellis encoding and decoding, 3) Reed Solomon encoding and decoding, and 4) MPEG compatibility.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 25, 2004
    Applicant: ATI Technologies Inc.
    Inventors: Christopher H. Strolle, Samir N. Hulyalkar, Jeffrey S. Hamilton, Haosong Fu, Troy A. Schaffer
  • Patent number: 6709528
    Abstract: A method of enhancing the corrosion resistance of an austenitic steel includes removing material from at least a portion of a surface of the steel such that corrosion initiation sites are eliminated or are reduced in number relative to the number resulting from processing in a conventional manner. Material may be removed from the portion by any suitable method, including, for example, grit blasting, grinding and/or acid pickling under conditions more aggressive than those used in conventional processing of the same steel.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: March 23, 2004
    Assignee: ATI Properties, Inc.
    Inventors: John F. Grubb, James D. Fritz, Ronald E. Polinski
  • Patent number: 6710819
    Abstract: A method and a system for improved filtering of display data is disclosed herein. A display system may be used to separately filter display components of the display data based on frequency content of the display components. The display system can include a display data source, a digital image processor, and a display. The display system receives display data from the display data source. The frequency content of a plurality of display components in the display data is determined by the digital image processor. The digital image processor filters the plurality of display components based on the associated frequency content. In at least one embodiment, display components having lower frequency content are filtered to minimize flicker, while display components having higher frequency content are filtered to maximize resolution. The filtered display data is then transmitted to the display.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 23, 2004
    Assignee: ATI Technologies, Inc.
    Inventor: Philip L. Swan