Abstract: A method for controlling two monitors on the basis of an input-side pixel data stream, in which one part of each line of the input-side pixel data stream is displayed on one of the monitors and another part of the line is displayed on another of the monitors, comprises the storing of one part of the line of the input-side pixel data stream in one FIFO memory device and the storing of the other part of the line of the input-side pixel data stream in another FIFO memory device. The readout of one FIFO memory device takes place with the pixel frequency with which one monitor is operated while the readout of the other FIFO memory device takes place with the pixel frequency with which the other monitor is operated. Thus, a moderately priced and high speed monitor control circuit is realized.

Abstract: First and second RF signals in the respective first and second channels of a multiple channel diversity receiver are processed jointly in a joint timing loop filter for baud clock recovery. The channel with the stronger signal determines the frequency of the baud clock for the channel with the weaker signal, leaving the respective PLL's to make individual phase adjustments for each channel. The first and second channels also share a skew corrector for baud clock recovery when the multipath delay between the first and second RF signals is greater than one whole baud clock period. The whole baud skew corrector computes the correlation between the first and second received signals, and if the correlation is low, shifts the first and second signals by one whole baud and recomputes the correlation. The process of shifting the first and second received signals and computing the correlation function is repeated for various whole baud shifts in accordance with a search strategy to find the best (highest) correlation.

Abstract: During a fast forward search of a multimedia presentation, the audio portion of the multimedia presentation is pitch-adjusted and played back in order to assist the user in determining where within the multimedia presentation the playback currently is located. In another embodiment, the audio playback portion of the multimedia presentation can be buffered such that only intermittent portions of the audio are played back in such a manner that is audible to an end user in determining where in the multimedia presentation the playback routine is located. Another embodiment accommodates a multimedia presentation being reversed will have its audio portion buffered and played back in forward in order to assist the user in determining where in the multimedia presentation the rewind currently is. In addition, an individual word detect can be performed during the rewind whereby each word is individually detected and played forward after its detection.

Abstract: A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.

Abstract: A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a plurality of media devices. A first multimedia program is routed from a first source device to a first destination device. The A/V server detects a conflict when a second source device attempts to route a second multimedia program to the first destination device. To resolve the conflict, the A/V server determines suitable media devices to process the second multimedia program. The A/V server may send the second program to a second destination device to process the second program in the same manner as the first destination device. Alternatively, the A/V server may send the second program to a destination device capable of recording the second program.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: The present invention includes a method and apparatus for graphics processing in a handheld device including a transform engine capable of receiving vertex information. The transform engine generates a plurality of vertices from the vertex information, wherein each of the vertices includes a corresponding bin identifier. The method and apparatus further includes view frame factors defining a clipping region such that when any of the plurality of vertices is within the clipping region, a clip identifier is generated for that vertex using the corresponding bin identifier. A vertex shader coupled to a clipping module, wherein the clipping module generates supplemental vertices and the vertex shader receives the supplemental vertices therefrom. The vertex shader combines the supplemental vertices with the bin identifiers and are provided to a vertex buffer.

Abstract: In accordance with the present invention, a write behind controller receives control information from a display device controller in order to determine a current location available in a frame buffer for receiving information. Write accesses of the frame buffer by a rendering engine are prohibited if the access is to an area below a currently available location of the frame buffer. Generally, the rendering engine will be stalled when the requested address location has not yet displayed its data. Subsequently, the write access to the frame buffer is allowed when location has been rastered.

Abstract: A video overlay switching apparatus and method utilizes a common video scaler that receives input video data. A programmable switching mechanism, such as a register-controlled multiplexer, receives video information from the video scaler, either scaled video or unscaled video, and selectively routes the video data to any one of a plurality of video overlay generators to facilitate selective display of overlay data on a specified display device. The programmable switching mechanism also facilitates programming of frame buffer space for each display engine, based on which video overlay generator has been selected to receive input video.

Abstract: A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geometric values based on the plurality of vertex values, wherein the differential geometric values are independent of a parameter slope between the plurality of vertex values. While in a calculation mode, a first geometric value and second geometric value are determined based on a pixel value, a plurality of vertex values and the differential geometric values. A pixel value is determined for each of the plurality of pixels based on the vertex parameter value, the first geometric value and the second geometric value. Thereupon, pixel parameters may be interpolated on a per-pixel basis reusing the differential geometric values.

Abstract: A method and apparatus for successive linear approximation to obtain a specific point on a non-linear monotonic function include processing that begins by obtaining a T-coordinate for the specific point. The specific point includes a T-coordinate and an N-coordinate. The process then continues by selecting a minimum point and a maximum point on the non-linear monotonic function to bound the specific point. The processing then continues by deriving a linear reference between the minimum and maximum points. The process then proceeds by obtaining a reference N-coordinate that lies on the linear reference based on the T-coordinate. The process then continues by determining a reference T-coordinate lying on the non-linear monotonic function based on the referenced N-coordinate. The process then continues by determining whether the referenced T-coordinate is substantially similar to the T-coordinate.

Abstract: An integrated circuit package includes a first or active substrate and a second or passive substrate. The active substrate includes at least one circuit that generates heat during circuit operation. The passive substrate does not include any heat-generating circuits, although the passive substrate may include passive, disabled or dormant circuitry. The two substrates are preferably fabricated of semiconductor material and have substantially equal coefficients of thermal expansion. The passive substrate is thermally coupled to the active substrate preferably using a thin layer of adhesive, such as an epoxy. The passive substrate serves to thermally conduct the heat generated by the circuits of the active substrate away from the active substrate. An internal metallic heat sink may be optionally thermally coupled to the passive substrate to further aid in the transfer of heat away from the active substrate.

Abstract: A circuit and method serves as a slave interface to support both register read/write and monitor detection operations by a graphics controller chip, or other display data source, with a plurality of display devices. The circuit supports differing monitor detection protocols including, for example, I2C protocol and non-DDC type protocols. The circuit may be set in two modes, a register mode and a bypass mode. The register mode is used to facilitate standard I2C protocol to a display device. Display detection bypass circuitry is used to selectively bypass the register based display detector interface by connecting input pins to any two of a plurality of I/O pins so that the system may be used for monitor detection of a plurality of different display devices, such as CRTs and LCDs to facilitate multiprotocol display detection.

Abstract: A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of corresponding independent clock signals to a number of different processing engines. A memory clock divider circuit and method selectively activates a plurality of independent clock signals in response to received condition data. In one embodiment, an engine clock source is also coupled through a switching circuit such that it is selectively output to one or more processing engines. The switching circuit disables the output from the engine clock based on register condition data. In another embodiment, a plurality of memory read latch circuits are controlled by a memory read latch control circuit. The memory read latch control circuit is operative to dynamically activate and deactivate the plurality of memory read latches based on detected memory read requests to facilitate memory access activity-based power reduction.

Abstract: A method and apparatus for determining a processing speed of an integrated circuit includes a first flip flop having an input port receiving an input signal, an output port providing a flip flop output signal and a timing port receiving an incoming clock signal. The method and apparatus further includes a delay circuit operably coupled to the output port of the first flip flop, such that the delay circuit receives the flip flop output signal, generating a delayed timing signal. Further included is at least one clock speed adjusting circuit operably coupled to the delay circuit and a multiplexer coupled to the at least one clock speed adjusting circuit and the delay circuit, wherein the multiplexer receives a select delay signal in a selective delay input port. Based on the select delay signal, a multiplexer output signal is chosen and provided to an input port of a second flip flop.

Abstract: A robotic tool changer with an improved safety interlock includes a master unit, a tool unit, and a coupler movable between coupled and decoupled positions and operative to couple the master and tool units. A circuit for actuating the coupler is associated with the tool unit, for connection to an interlock that closes when the tool is safely parked in a tool stand. The circuit enables the coupler to assume the decoupled position when the master and tool units are coupled and the circuit is closed. The robotic tool changer additionally includes a circuit operative to enable the coupler to assume the decoupled position when the master unit is decoupled from the tool unit.

Abstract: An input output ring for a semiconductor device is disclosed that uses power buffers having widths that vary from the widths of the input and output buffers. In one embodiment, the pitches between bond pads are the same, in another embodiment the pitches between the bond pads can vary. In another embodiment, the number of bond pads is greater than the number of associated active buffer areas. By connecting two power bond pads to a common buffer the inductance associated with the buffer is reduced, thereby reducing the number of active buffers needed to be dedicated to providing power to the semiconductor device.

Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.