Abstract: A technique for approximating output values of a function based on LaGrange polynomials is provided. Factorization of a LaGrange polynomial results in a simplified representation of the LaGrange polynomial. With this simplified representation, an output value of a function may be determined based on an input value comprising a fixed point input mantissa and an input exponent. Based on a first portion of the fixed point input mantissa, a point value and at least one slope value are provided. At least one slope value is based on a LaGrange polynomial approximation of the function. Thereafter, the point value and the at least one slope value are combined with a second portion of the fixed point input mantissa to provide an output mantissa. Based on this technique, a single set of relatively simple hardware elements may be used to implement a variety of functions with high precision.

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

Abstract: A method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer is presented. The custom memory includes a memory array that stores the frame buffer as well as a data path that performs at least a portion of the blending operations associated with pixel fragments generated by a graphics processor. The fragments produced by a graphics processor are oversampled fragments such that each fragment may include a plurality of samples. If the sample set for a particular pixel location can be compressed, the compressed sample set is stored within the frame buffer of the custom memory circuit. However, if such compression is not possible, pointer information is stored within the frame buffer on the custom memory, and a sample memory controller included on the graphics processor maintains a complete sample set for the pixel location within a sample memory.

Abstract: A system and methods are shown for improved processing of motion compensated video. A software driver handles image data related to motion compensated video. The image data includes IDCT coefficients and motion compensation vector data. A unique identifier is attached to the image data, preserving the relationship between the IDCT coefficients and motion compensated vector data related to an image block. The software driver sends the IDCT coefficients to an IDCT component. The IDCT coefficients are processed and an interrupt is sent to the software driver including the unique identifier of the processed IDCT coefficients. The software driver sends the motion compensation vector data related to the unique identifier in the interrupt. A 3D pipe receives the motion compensation vector data and reads the corresponding processed IDCT data.

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract: First and second RF signals in the respective first and second channels of a multiple channel diversity receiver are processed jointly in a joint timing loop filter for baud clock recovery. The channel with the stronger signal determines the frequency of the baud clock for the channel with the weaker signal, leaving the respective PLL's to make individual phase adjustments for each channel. The first and second channels also share a skew corrector for baud clock recovery when the multipath delay between the first and second RF signals is greater than one whole baud clock period. The whole baud skew corrector computes the correlation between the first and second received signals, and if the correlation is low, shifts the first and second signals by one whole baud and recomputes the correlation. The process of shifting the first and second received signals and computing the correlation function is repeated for various whole baud shifts in accordance with a search strategy to find the best (highest) correlation.

Abstract: A method for controlling two monitors on the basis of an input-side pixel data stream, in which one part of each line of the input-side pixel data stream is displayed on one of the monitors and another part of the line is displayed on another of the monitors, comprises the storing of one part of the line of the input-side pixel data stream in one FIFO memory device and the storing of the other part of the line of the input-side pixel data stream in another FIFO memory device. The readout of one FIFO memory device takes place with the pixel frequency with which one monitor is operated while the readout of the other FIFO memory device takes place with the pixel frequency with which the other monitor is operated. Thus, a moderately priced and high speed monitor control circuit is realized.

Abstract: During a fast forward search of a multimedia presentation, the audio portion of the multimedia presentation is pitch-adjusted and played back in order to assist the user in determining where within the multimedia presentation the playback currently is located. In another embodiment, the audio playback portion of the multimedia presentation can be buffered such that only intermittent portions of the audio are played back in such a manner that is audible to an end user in determining where in the multimedia presentation the playback routine is located. Another embodiment accommodates a multimedia presentation being reversed will have its audio portion buffered and played back in forward in order to assist the user in determining where in the multimedia presentation the rewind currently is. In addition, an individual word detect can be performed during the rewind whereby each word is individually detected and played forward after its detection.

Abstract: A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: A system and methods are provided for resolving resource conflicts related to processing multiple media streams on a single media device. An audio/video (A/V) server is used to interconnect a plurality of media devices. A first multimedia program is routed from a first source device to a first destination device. The A/V server detects a conflict when a second source device attempts to route a second multimedia program to the first destination device. To resolve the conflict, the A/V server determines suitable media devices to process the second multimedia program. The A/V server may send the second program to a second destination device to process the second program in the same manner as the first destination device. Alternatively, the A/V server may send the second program to a destination device capable of recording the second program.

Abstract: The present invention includes a method and apparatus for graphics processing in a handheld device including a transform engine capable of receiving vertex information. The transform engine generates a plurality of vertices from the vertex information, wherein each of the vertices includes a corresponding bin identifier. The method and apparatus further includes view frame factors defining a clipping region such that when any of the plurality of vertices is within the clipping region, a clip identifier is generated for that vertex using the corresponding bin identifier. A vertex shader coupled to a clipping module, wherein the clipping module generates supplemental vertices and the vertex shader receives the supplemental vertices therefrom. The vertex shader combines the supplemental vertices with the bin identifiers and are provided to a vertex buffer.

Abstract: In accordance with the present invention, a write behind controller receives control information from a display device controller in order to determine a current location available in a frame buffer for receiving information. Write accesses of the frame buffer by a rendering engine are prohibited if the access is to an area below a currently available location of the frame buffer. Generally, the rendering engine will be stalled when the requested address location has not yet displayed its data. Subsequently, the write access to the frame buffer is allowed when location has been rastered.

Abstract: A video overlay switching apparatus and method utilizes a common video scaler that receives input video data. A programmable switching mechanism, such as a register-controlled multiplexer, receives video information from the video scaler, either scaled video or unscaled video, and selectively routes the video data to any one of a plurality of video overlay generators to facilitate selective display of overlay data on a specified display device. The programmable switching mechanism also facilitates programming of frame buffer space for each display engine, based on which video overlay generator has been selected to receive input video.

Abstract: A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geometric values based on the plurality of vertex values, wherein the differential geometric values are independent of a parameter slope between the plurality of vertex values. While in a calculation mode, a first geometric value and second geometric value are determined based on a pixel value, a plurality of vertex values and the differential geometric values. A pixel value is determined for each of the plurality of pixels based on the vertex parameter value, the first geometric value and the second geometric value. Thereupon, pixel parameters may be interpolated on a per-pixel basis reusing the differential geometric values.

Abstract: A method and apparatus for successive linear approximation to obtain a specific point on a non-linear monotonic function include processing that begins by obtaining a T-coordinate for the specific point. The specific point includes a T-coordinate and an N-coordinate. The process then continues by selecting a minimum point and a maximum point on the non-linear monotonic function to bound the specific point. The processing then continues by deriving a linear reference between the minimum and maximum points. The process then proceeds by obtaining a reference N-coordinate that lies on the linear reference based on the T-coordinate. The process then continues by determining a reference T-coordinate lying on the non-linear monotonic function based on the referenced N-coordinate. The process then continues by determining whether the referenced T-coordinate is substantially similar to the T-coordinate.

Abstract: An integrated circuit package includes a first or active substrate and a second or passive substrate. The active substrate includes at least one circuit that generates heat during circuit operation. The passive substrate does not include any heat-generating circuits, although the passive substrate may include passive, disabled or dormant circuitry. The two substrates are preferably fabricated of semiconductor material and have substantially equal coefficients of thermal expansion. The passive substrate is thermally coupled to the active substrate preferably using a thin layer of adhesive, such as an epoxy. The passive substrate serves to thermally conduct the heat generated by the circuits of the active substrate away from the active substrate. An internal metallic heat sink may be optionally thermally coupled to the passive substrate to further aid in the transfer of heat away from the active substrate.

Abstract: A circuit and method serves as a slave interface to support both register read/write and monitor detection operations by a graphics controller chip, or other display data source, with a plurality of display devices. The circuit supports differing monitor detection protocols including, for example, I2C protocol and non-DDC type protocols. The circuit may be set in two modes, a register mode and a bypass mode. The register mode is used to facilitate standard I2C protocol to a display device. Display detection bypass circuitry is used to selectively bypass the register based display detector interface by connecting input pins to any two of a plurality of I/O pins so that the system may be used for monitor detection of a plurality of different display devices, such as CRTs and LCDs to facilitate multiprotocol display detection.

Abstract: A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of corresponding independent clock signals to a number of different processing engines. A memory clock divider circuit and method selectively activates a plurality of independent clock signals in response to received condition data. In one embodiment, an engine clock source is also coupled through a switching circuit such that it is selectively output to one or more processing engines. The switching circuit disables the output from the engine clock based on register condition data. In another embodiment, a plurality of memory read latch circuits are controlled by a memory read latch control circuit. The memory read latch control circuit is operative to dynamically activate and deactivate the plurality of memory read latches based on detected memory read requests to facilitate memory access activity-based power reduction.