Abstract: In one embodiment, an automatic multichannel equalization control system uses programmable multichannel templates containing equalization control values for a programmable multichannel audio processor that selectively controls each channel of multichannel audio using the equalization control values. The system also optionally uses an adaptive equalization template interface to facilitate input of user presets that are incorporated in the stored equalization templates for each audio medium. When the audio medium's identification number (ID) is read from the medium header or a particular track, the system selects the appropriate equalization template preset by the user and programs the programmable multichannel audio processor (equalizer) to effect desired audio output.

Abstract: In a specific embodiment of the present invention RGB video data is converted to a YUV video data representation. The YUV video data is compressed and transmitted over a data bus to a memory device. Also transmitted is a compression indicator. The memory device buffers arid decompresses the compressed data. The decompressed data is converted back into uncompressed RGB video, and stored in a memory array. During a read cycle, the RGB data is converted into YUV video data, and compressed at the memory before being transmitted to the graphics processor along with a compression indicator. The graphics processor decompresses the data and provides it to the requesting client.

Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.

Abstract: A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.

Abstract: A configurable buffer has two storage areas. Depending upon a state of a buffer control signal, the two storage areas are configured to buffer a single stream of data together or to buffer two streams of data separately. In an exemplary video graphics processing application, one stream of data includes pass-through values of fragments being rendered (e.g. color, location, and/or depth values) and the other stream of data includes corresponding displaced (or otherwise perturbed) texture coordinate pairs. Such a buffer may be used to reduce the amount of buffer storage needed to support both single-pass and multipass operations in a pixel pipeline.

Abstract: A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.

Abstract: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across at least one of the electrical leads associated with the carrier substrate.

Abstract: A method and system connects a display device or other device to a computer system during operation of the system. Initially a run time EDID (Extended Display Identification Data) flag is set to a first value indicating no run time EDID is required. By monitoring for an interrupt a checking is carried out for a change to a new display device in the computer system. If no change to a new display device is detected, the run time EDID flag is checked. If the run time EDID flag indicates that no run time EDID is required, an EDID is read from a video BIOS on a graphics adapter in the computer system. If the run time EDID flag indicates that a run time EDID is required, an EDID is read from a video memory on a graphics adapter in the computer system. If a change to a new display device is detected, the run time EDID flag is set to a second value and EDID is then downloaded from the new display device.

Abstract: A method and apparatus for indexing and locating key frames in streaming frame data and variable-frame-length data is described. Fast and efficient location of desired key frames in both directions (e.g., forward/backward, future/past) is provided. An estimate of the distance to the desired key frame is made and a seek performed according to that distance. At the location specified by the seek, key frame seek assist data are obtained. The desired key frame is located or a new seek is performed, depending on the key frame seek assist data obtained. By placing the key frame seek assist data at readily identifiable locations, efficient location of key frames is provided. The key frame seek assist data may be tailored to optimize efficiency for seeking in a particular direction, for example, backwards. The seek process is correspondingly configured to favor seeking in the more efficient direction.

Abstract: A method and apparatus for optimizing production yield and operational performance of integrated circuits is provided. A nominal operating voltage is used to categorize integrated circuits into a plurality of performance categories, and the nominal operating voltage is adjusted for each performance category to optimize the yield within that performance category. Integrated circuits may be operated at different operating rates according to their performance categories. The operating rates of an integrated circuit may be controlled by programming a clock register for the integrated circuit. Correct programming of the clock register may be assured by programming a one-time-programmable device. A one-time-programmable device may also be used to program the nominal operating voltage once the optimal nominal operating voltage has been determined. A diagnostic program may be used to select optimum performance parameters for an integrated circuit.

Abstract: An address generator provides for generation of addresses for a plurality of different tests by allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address generator. Embodiments of the present invention utilize the address values to generate data values to be stored in a memory under test. Likewise, an expected data value is generated and compared to the stored value. A data comparator verifies the stored data to the expected value. A single latch stores compare results for a plurality of memory locations.

Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: The television system for displaying images on a television display has a source of a series of video fields. An active de-interlacer receives first field data from a first field of the series of video fields and second field data from a second field of the series of video fields, and produces de-interlaced data and control data. A format converter has a vertical scaler then directly receives the de-interlaced data and produces vertically scaled data therefrom. The format converter also has a re-interlacer that receives the vertically scaled data and the control data, and produces a re-interlaced frame. A horizontal scaler is connected to receive the re-interlaced frame and to produce therefrom a horizontally scaled re-interlaced frame. Display drivers receive the horizontally scaled re-interlaced fame and produce therefrom television display signals for forming images on a television, a high definition television of other type of television display.

Abstract: A robotic crash protection device is adapted to be interposed between a robot arm and a robotic tool for detecting a crash. The device includes a housing, a piston having a generally central bore movably mounted within the housing, an actuator for engaging the piston and moving the piston in response to a crash, and a switch disposed within the housing and generally aligned with the bore of the piston. The switch contacts are disposed such that in a default position the bore of the piston engages the contacts and maintains the contacts in one switch state, and in the event of a crash the piston moves and permits the contacts to assume the opposite switch state. A non-circular contact surface between the actuator and the piston ensures a consistent response to lateral forces applied in to the axial direction in any radial direction.

Abstract: An unused logic portion of a device is identified, where the unused logic portion of the device is part of a metal definable logic portion of the device. The unused logic portion is specified to be used as a bypass capacitor between a first and second power node.

Abstract: A method and apparatus for parallel processing of geometric aspects of video graphics data include processing that begins by determining whether an object-element is within a clipped volume. The processing continues by determining whether the object-element is to be clipped when it is within the clipped volume. The processing then continues by performing in parallel, a clipping function and an attribute derivation function upon the object-element when the object-element is to be clipped. The attribute derivation function may include performing a light function, texture map function, etc.

Abstract: A method and apparatus for motion estimation for encoding sequential frames is described. One embodiment of the invention provides efficiency by checking only four points surrounding a given point. Scores may be calculated corresponding to a level of difference between the given point in a reference frame and the points in a candidate frame. The efficiency may be further enhanced by storing scores of previously examined points for later use. The scores may be stored in a table. The table may be initialized to have invalid scores or scores corresponding to a great difference along search window boundaries to prevent searching outside of the search window boundaries. One embodiment of the invention implements a sliding window technique for efficient computation.

Abstract: An improved deinterlacing technique reconstructs regions of an image that change monotonically in the vertical direction (i.e., vertical deinterlacing). The present invention adapts to the image content without using spatio-temporal interpolation techniques. Rather, deinterlacing in accordance with the teachings of the present invention uses, for example, four localized input pixel values to produce an output pixel value that minimizes spatial artifacts (i.e., accurately reconstructs regions that change monotonically in the vertical direction). In another embodiment, an overlay scaler shares overlay scaling circuitry and deinterlacing circuitry to provide a cost effective implementation of a unique deinterlacing circuit. In another embodiment, a plurality of offsets are used in addition to three or more pixels.

Abstract: A method and apparatus for processing DVD video data and sub-picture data is accomplished by storing a line of DVD video data and at least a partially decoded portion of DVD sub-picture data. The partially decoded DVD sub-picture data is still in an encoded format, which may be two bits per pixel, but line information has been decoded from the DVD subpicture data stream. Once stored, the DVD video data is retrieved from the memory and scaled to produce scaled video data. Similarly, the partially decoded sub-picture data is retrieved from memory, further decoded, and scaled to produce scaled sub-picture data. The scaled video data is blended with the scaled sub-picture data to produce a video output.

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.