Abstract: An approximation circuit approximates a function f(x) of an input value “x” by adding at least the first two terms in a Taylor series (i.e., f(a) and f′(a)(x−a)) where “a” is a number reasonably close to value “x”. The first term is generated by a first look-up table which receives the approximation value “a”. The first look-up table generates a function f(a) of the approximation value “a”. The second look-up table generates a first derivative f′(a) of the function f(a). A first multiplier then multiplies the first derivative f′(a) by a difference (x−a) between input value “x” and approximation value “a” to generate a product f′(a)(x−a). The approximation circuit can approximate the function f(x) by adding the third term of the Taylor series, (½)f″(a)(x−a)2.

Abstract: A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.

Abstract: A method for assuring that samples are always available for transmission when a modern is implemented as a process executing in the memory of a host computer. The modem process converts, digital information into transmit data samples. In the absence of digital information, the modem process converts fill data into fill data samples. The transmit data samples and fill data samples are stored in a segmented buffer for transmission to a remote modem. If additional transmit data samples become available and the buffer contains fill data samples which have not been transmitted to the remote modem, the modem process replaces the fill data samples in the buffer with the additional transmit data samples. The method helps assure that samples are always available for transmission, and simultaneously reduces the time delay or latency between when data enter the modem and when the data are subsequently transmitted.

Abstract: A method for producing a stainless steel with improved corrosion resistance includes homogenizing at least a portion of an article of a stainless steel including chromium, nickel, and molybdenum and having a PREN of at least 50, as calculated by the equation: PREN=Cr+(3.3×Mo)+(30×N), where Cr is weight percent chromium, Mo is weight percent molybdenum, and N is weight percent nitrogen in the steel. In one form of the method, at least a portion of the article is remelted to homogenize the portion. In another form of the method, the article is annealed under conditions sufficient to homogenize at least a surface region of the article. The method of the invention enhances corrosion resistance of the stainless steel as reflected by the steel's critical crevice corrosion temperature.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: In accordance with an embodiment of the present invention a digital representation of a YCbCr video signal data stream is received that represents a video image or a series of video images. Received Y data values are linearly transformed and used to provide an RGB signal. The RGB signal is non-linearly adjusted to provide an adjusted RGB signal that enhances the viewed brightness of the data. In a specific embodiment, the non-linear adjusting adjusts the brightness of data near a mid-range of the video image more than other ranges of data.

Abstract: A method and apparatus for video compression that provides support for the inclusion of VBI data and copy protection data in an enhanced encoded video data stream is presented. A received video signal is separated such that a video data stream and a VBI data stream are produced. The video data stream is encoded to produce a compressed video data stream. The various types of VBI data that may be included in the VBI data stream are isolated, and one or more are selected for inclusion in the enhanced video data stream. The compressed video data stream is then combined with the one or more VBI data type streams to produce the enhanced video data stream. In other embodiments, copy protection information in the video signal is also detected and encoded such that it also can be included in the enhanced video data stream. The enhanced video data stream can be stored in memory or some other type of storage media for retrieval at a later time.

Abstract: A lighting effect computation block and method therefore is presented. The lighting effect computation block separates lighting effect calculations for video graphics primitives into a number of simpler calculations that are performed in parallel but accumulated in an order-dependent manner. Each of the individual calculations is managed by a separate thread controller, where lighting effect calculations for a vertex of a primitive may be performed using a single parent light thread controller and a number of sub-light thread controllers. Each thread controller manages a thread of operation codes related to determination of the lighting parameters for the particular vertex. The thread controllers submit operation codes to an arbitration module based on the expected latency and interdependency between the various operation codes. The arbitration module determines which operation code is executed during a particular cycle, and provides that operation code to a computation engine.

Abstract: A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of memory clients in the video graphics system. Based on this determination, a plurality of timers are configured, wherein each of the timers corresponds to one of the plurality of memory clients. The timers associated with the memory clients store two values. One value indicates the memory access interval for the corresponding client, which determines the spacing between memory access requests that can be issued by that particular client. The other value stored in the time is a memory access limit value, which determines the maximum length of a protected access to the memory by that particular client. A memory controller in the system receives requests from the plurality of clients and determines the priority of the different requests.

Abstract: A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as “masters”). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements. A sort queue may be used to reorder the requests.

Abstract: A service chip for use with a computer. The chip includes a CPU interface, a transceiver interface, an adaptive echo cancellation filter, a monitor, and first and second data synthesizers. The CPU interface receives a transmit sample sequence from a modem sample generator executing on a central processor of the computer, and presents a receive sample sequence to a modem sample receiver executing on the central processor. The transceiver interface presents data to a line interface, which includes digital-to-analog and analog-to-digital converters for converting samples to/from analog signals for transmission on a telephone line. The filter adapts in response to an echo correlation between data transmitted over a transmit channel of the modem and data received on a receive channel of the transceiver interface. The monitor monitors the transmit sample sequence for a data starvation condition.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.

Abstract: A video graphics adapter is configured to provide both parallel and sequential color components to separate display monitors. When in a first state, the video graphics adapter provides individual color components to a video-output independent of each other color component, such that an entire frame of a red component will be provided to a video-out port for prior to, or subsequently after, an entire frame of the green component being provided to the video-out port. Each color component is provided to a common port. In response to a second configuration state, a traditional parallel red, green, blue (RGB) data port will be generated in order to provide data to a display device. In yet another configuration state, both the individual color components are provided at a common port, and the individual color components are provided in parallel to an RGB port.

Abstract: Multiple graphic images are generated simultaneously. An object or a polygon is received by a 3D graphics pipeline whereby a first stage of the pipeline performs a world transform on the modeling space of the object or polygon. An object culling is performed on the world space to eliminate objects not within view. Lighting is applied to the object as appropriate. Two view transforms are performed in parallel. Backface culling is applied to the resulting data. A single backface culling algorithm can be applied to both of the view transform scenes. A projection transformation is applied to those objects remaining following the backface culling. The first and second view transformed scenes are rendered in order to produce a first target image and a second target image respectively.

Abstract: A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

Abstract: A configurable vertex blending circuit that allows both morphing and skinning operations to be supported in dedicated hardware is presented. Such a configurable vertex blending circuit includes a matrix array that is used for storing the matrices associated with the various portions of the vertex blending operations. Vertex data that is received is stored in an input vertex buffer that includes multiple position buffers such that the multiple positions associated with morphing operations can be stored. Similarly, the single position typically associated with skinning operations can be stored in one of the position buffers. The input vertex buffer further stores blending weights associated with the various component operations that are included in the overall vertex blending operation. An arithmetic unit, which is configured and controlled by a transform controller, performs the calculations required for each of a plurality of component operations included in the overall vertex blending operation.

Abstract: A duplex stainless steel including, in weight percent, up to 0.06 percent carbon, 15 up to less than 25 percent chromium, greater than 3 up to 6 percent nickel, up to 3.75 percent manganese, 0.14 up to 0.35 percent nitrogen, up to 2 percent silicon, greater than 1.4 up to less than 2.5 percent molybdenum, up to less than 0.5 percent copper, up to less than 0.2 percent cobalt, up to 0.05 percent phosphorous, up to 0.005 percent sulfur, and 0.001 up to 0.0035 percent boron, with the remainder being iron and incidental impurities is disclosed. The duplex stainless steel may be included in an article of manufacture, such as a strip, bar, plate, sheet, casting, tubing or piping. A method for making such a duplex stainless steel is also disclosed.

Abstract: A method and apparatus for displaying 3-D stereoscopic images is disclosed. A first stencil is used to filter a right eye image. A second stencil is used to filter a left eye image. Generally, the first and second stencil will have mutually exclusive active areas. The filtered left eye image and filtered right eye image are combined to form a single 3-D image having both images. The combined image is displayed on a conventional monitor, and viewed through the use of a pair or 3-D blue/red type lenses.

Abstract: A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.