Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.

Abstract: Methods and apparatus of generating a refined reference frame for inter-frame encoding by applying blur parameters to allow encoding of image frames having blurred regions are presented herein. The methods and apparatus may identify a blurred region of an image frame by comparing the image frame with a reference frame, generate a refined reference frame by applying the blur parameter indicative of the blurred region to the reference frame, determine whether to use one of the reference frame and refined reference frame to encode the image frame, and encode the image frame using the refined reference frame when determined to use the refined reference frame.

Abstract: A track-module apparatus comprising: (a) idler-arm axle structure for a vehicle and having leading and trailing idler-arm axles; (b) a leading idler arm rotatably attached to the leading idler-arm axle and extending forwardly to a leading-arm distal end at which a leading ground-engaging idler wheel is rotatably attached and rearwardly to a rearward suspension end; (c) a trailing idler arm rotatably attached to the trailing idler-arm axle and extending rearwardly to a trailing-arm distal end at which a trailing ground-engaging idler wheel is rotatably attached and forwardly to a forward suspension end; (d) bogie-axle structure (i) affixed to one of the idler arms, (ii) having at least one bogie-arm axle, and (iii) positioning the at least one bogie-arm axle adjacent to and below the idler-arm axle of the idler arm to which it is affixed; (e) leading-arm and trailing-arm suspension elements rotatably attached to and extending downwardly from the rearward and forward suspension ends, respectively, and each havi

Abstract: A manually-rotatable hubcap for wheel/axle apparatus, the wheel configured to rotate with respect to the axle and having a wheel inner surface substantially parallel to the axle, the hubcap comprising: (a) a hubcap body having a lubrication filling port and a sealing surface facing the wheel inner surface; (b) retention structure for attaching the hubcap body to the wheel; and (c) a seal between the sealing surface and the wheel inner surface.

Abstract: A technique for determining an adaptive quantization parameter offset for a block of encoded video includes obtaining a rate control factor for the quantization parameter, determining a content-based quantization parameter factor for the quantization parameter, determining an adaptive variance based quantization offset based on content-based quantization parameter factors for a frame prior to the current frame, and combining the rate control factor, the content-based quantization parameter factor, and the adaptive offset to generate the quantization parameter.

Abstract: A memory module performs a memory readiness test, and reports results to a host system. The memory module initializes a status register with an initial ready time value and a memory readiness status. The memory module conducts the memory readiness test, and while conducting the memory readiness test, estimates a new ready time based on the progress of the memory readiness test. The memory module updates the ready time value in the status register based on the new ready time. After finishing the memory readiness test, the memory module updates the memory readiness status in the status register.

Abstract: A technique for generating encoded video in a client-server system is provided. According to the technique, a server determines that reprojection analysis should occur. The server generates reprojection metadata based on suitability of video content to reprojection. The server generates encoded video based on the reprojection metadata, and transmits the encoded video to a client for display. The client reprojects video content as directed by the server.

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.

Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

Abstract: Systems, apparatuses, and methods for calculating a quantization parameter (QP) for encoding video frames to meet a given bit budget are disclosed. Control logic coupled to an encoder calculates a complexity indicator that represents a level of difficulty in encoding a previous video frame. The complexity indicator is based at least in part on a first parameter associated with the previous video frame and corresponds to one or more of a variance, an intra-prediction factor, and an inter-to-intra ratio. The complexity indicator is then used by the control logic to calculate a preferred QP to use to encode the current video frame to meet a given bit budget. By using the preferred QP generated based on the complexity indicator, the encoder is able to make fewer QP adjustments during the frame. This helps to improve the visual quality of the resulting encoded video bitstream.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

Abstract: A processing unit includes a processor core that implements a physical function that supports multiple virtual functions. The processing unit includes a bus interface that supports communication between an external bus and the physical and virtual functions implemented using the processor core. During a reset of the processing unit, power is interrupted to the processor core power to the bus interface is maintained. The bus interface responds to requests for the physical and virtual functions received over the external bus concurrently with the power interruption. The bus interface responds based on state information associated with the virtual function. Power is restored to the processor core in response to the reinitialization of the GPU. The bus interface stops responding to requests for the physical and virtual functions received over the bus interface in response to restoring the power to the processor core and forwards requests received over the external bus from the bus interface to the processor core.

Abstract: A non-limiting embodiment of a titanium alloy comprises, in percent by weight based on total alloy weight: 5.1 to 6.5 aluminum; 1.9 to 3.2 tin; 1.8 to 3.1 zirconium; 3.3 to 5.5 molybdenum; 3.3 to 5.2 chromium; 0.08 to 0.15 oxygen; 0.03 to 0.20 silicon; 0 to 0.30 iron; titanium; and impurities. A non-limiting embodiment of the titanium alloy comprises an intentional addition of silicon in conjunction with certain other alloying additions to achieve an aluminum equivalent value of at least 6.9 and a molybdenum equivalent value of 7.4 to 12.8, which was observed to improve tensile strength at high temperatures.

Abstract: An electronic device for decompressing compressed data includes a decoding subsystem having a symbol decoder and a second symbol resolver with a number of local symbol decoders and a symbol selector. The symbol decoder decodes a first symbol from a first code for which a symbol is available in a block of the compressed data and communicates a length of the code to the second symbol resolver. Each local symbol decoder, substantially in parallel with the decoding of the first symbol in the symbol decoder, decodes a respective symbol from a first code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver selects, as a second symbol, based on the length received from the symbol decoder, one of the respective symbols from the local symbol decoders. The decoding subsystem then provides the first and second symbols.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.