Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.

Abstract: Various methods and apparatus for graphics processing are disclosed. In one aspect, a method of graphics processing using a computing system is provided. The method includes booting the computing system. After booting the computing system operating video memory of the computing system at a non-overclocked frequency, and prior to rebooting having the computing system sequentially increment the frequency of video memory by a selected change in frequency through a series of overclocked frequencies, after each frequency incrementing writing data to the video memory and testing the stability of the video memory data writing, and if the stability testing fails then decrementing the frequency of the video memory to a previous overclocked frequency at which the stability testing did not fail.

Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.

Abstract: Described is a system and method for dynamically changing encode quality at a block level based on runtime pre-encoding analysis of content in a video stream. A video encoder continuously analyzes the content during runtime, and collects statistics and/or characteristics of the content before encoding it. This classifies the block among pre-defined categories of content, where every category has its own compression parameters.

Abstract: Systems, apparatuses, and methods for remotely adjusting performance and power parameters of a computing device are disclosed. A computing system includes a first computing device connected to a second (remote) computing device. The user uses the second computing device to monitor and adjust parameters, such as a fan speed for a GPU on a video graphics card in the first computing device, while the first computing device executes a parallel data application such as a video game. Additionally, the user uses the second computing device to manage video recorder operations. By using the second computing device to send commands to a graphics driver and a video recorder application, the first computing device's display monitor does not display a user interface during execution of the video game. No video rendering is performed by the video graphics card of the first computing device to generate and control the user interface.

Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

Abstract: A hybrid co-processing system including both complex instruction set computer (CISC) architecture-based processing clusters and reduced instruction set computer (RISC) architecture-based processing clusters includes a parser to derive from a hardware configuration specific to the CISC architecture, such as an ACPI table, a device tree specific to the RISC architecture for booting. The hardware configuration information indicated by the device tree is specific to the RISC architecture, and in different cases includes more, less, or revised information than a corresponding ACPI table for the same hybrid co-processing system.

Abstract: An axially and radially compliant deburring tool holds a commercially available end tool holder, which in turn holds a variety of commercially available interchangeable deburring end tools, such as those commercially available for the hand deburring market. The axially and radially compliant deburring tool exhibits axial compliance in response to an external force by allowing a longitudinal sleeve holding the end tool holder to move longitudinally along a longitudinal axis of the tool, against a bias force. The axially and radially compliant deburring tool exhibits radial compliance in response to an external force by interaction between a cam contact member and a concave cam surface, both under the bias force and hence operative to return the commercially available to a centered, extended position in the absence of external forces.

Abstract: According to one embodiment, an alpha-beta titanium alloy comprises, in weight percentages: an aluminum equivalency in the range of about 6.7 to 10.0; a molybdenum equivalency in the range of 0 to 5.0; at least 2.1 vanadium; 0.3 to 5.0 cobalt; titanium; and incidental impurities.

Abstract: Various codecs and methods of using the same are disclosed. In one aspect, a method of processing video data is provided that includes encoding or decoding the video data with a codec in aggressive deployment and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re-decoding the video data in a non-aggressive deployment or generating a skip picture.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: A technique for determining a quality value for a subject block of encoded video is provided. Contributing blocks, of the same frame and/or different frames of the subject block, are determined by identifying blocks likely to be a part of the same moving object or background as the subject block. A spatial and/or temporal filter is then applied to the quality values of the contributing blocks and an initial quality value of the subject block. With a spatial filter, quality values for contributing blocks from the same frame are combined and used to modify the quality value of the subject block. With a spatial filter, a temporal characteristic quality value for contributing blocks of one or more other frames (such as the immediately previous frame) is determined and then combined with a quality value representative of the subject block.

Abstract: Techniques are provided herein for processing video data. The techniques include generating predicted macroblock coding modes for a set of macroblocks of a frame, assigning quantization parameters to the macroblocks based on the predicted macroblock coding modes, and encoding the set of macroblocks based on the quantization parameters.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: An encoder encodes pixels representative of a picture in a multimedia stream, generates a first approximate signature based on approximate values of pixels in a reconstructed copy of the picture, and transmits the encoded pixels and the first approximate signature. A decoder receives a first packet including the encoded pixels and the first approximate signature, decodes the encoded pixels, and transmits a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels. If a corrupted packet is detected, the multimedia application requests an intra-coded picture in response to the first approximate signature differing from the second approximate signature. The second signal instructs the decoder to bypass requesting an intra-coded picture and to continue decoding received packets in response to the first approximate signature being equal to the second approximate signature.

Abstract: Various audio encoders and methods of using the same are disclosed. In one aspect, an apparatus is provided that includes an audio encoder and an audio encoder mode selector. The audio encoder mode selector is operable to analyze video data and adjust an encoding mode of the audio encoder based on the analyzed video data.

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

Abstract: A robotic tool changer includes a locking mechanism that enhances safety. More particularly, the locking mechanism is an “over center” locking mechanism that maintains a constant lock force on a tool. The lock force exerted on the tool by the locking mechanism remains substantially constant, even after a motor providing power to the robotic tool changer is removed, and after the robotic tool changer experiences mechanical wear.