Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

Abstract: A memory module performs a memory readiness test, and reports results to a host system. The memory module initializes a status register with an initial ready time value and a memory readiness status. The memory module conducts the memory readiness test, and while conducting the memory readiness test, estimates a new ready time based on the progress of the memory readiness test. The memory module updates the ready time value in the status register based on the new ready time. After finishing the memory readiness test, the memory module updates the memory readiness status in the status register.

Abstract: A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.

Abstract: Disclosed herein is a region-based reference management system using in video frame encoding. Source content, such as video game streaming or remote desktop sharing, that includes scene changes or significant instantaneous changes in a region from one frame to the next can present encoding challenges. Techniques disclosed herein use hints about changes in regional frame content, dissect frame content into regions, and associate the dissected regions with stored reference frame data using the hints and information about the regions to more efficiently encode frames.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for improving performance of a data compression system is provided. The technique is applicable to compressed data sets that include compression blocks. Each compression block may be either compressed or uncompressed. Metadata indicating whether compression blocks are actually compressed or not is stored. If compression blocks are not compressed, then a read-decompress-modify-compress-write pipeline is bypassed. Instead, a compression unit writes the data specified by the partial request into the compression block, without reading, decompressing, modifying, recompressing, and writing the data, resulting in a much faster operation.

Abstract: Systems, methods, and devices for scene change detection and image encoding. A sequence of image frames is input. For a first image frame of the sequence, a first total sum of absolute transformed differences (SATD) is calculated. For a second frame of the sequence, a second total SATD is calculated. An absolute difference between the first total SATD and the second total SATD is calculated. If the absolute difference meets or exceeds a threshold, the second frame and a third frame of the sequence subsequent to the second frame are encoded based on a scene change, and the second frame and the third frame are transmitted. If the absolute difference does not meet or exceed the threshold, the second frame is encoded based on a same scene and the second frame is transmitted.

Abstract: Methods and apparatus provide pixel information for display. In one example, the methods and apparatus map, using a computing device, pixel information of a virtual rendering surface to a physical curved display screen based on field-of-view point reference data and display curvature data of one or more curved displays using a non-constant scale ratio among a plurality of differing physical pixels in at least one row of a portion of the physical curved display screen. Display data is output based on the mapped pixel information for display to the one or more curved displays.

Abstract: In an inherently safe robotic tool changer, a master unit couples to a tool unit via a first power source, and decouples from the tool unit using a separate, second power source. The second power source is only available when an attached tool is safely disposed in a tool stand. In embodiments where the first power source is not selectively applied, such as the constant bias provided by a spring, a detent mechanism maintains the master unit in a decoupled state when the master unit is removed from the tool unit. The detent mechanism allows the master unit to couple to a different tool unit upon physically abutting the new tool unit.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: A method and apparatus adaptively creates a dropped frame rate converted frame from a plurality of source frames using at least one alternate support frame in lieu of a neighboring source frame, in response to corrupted picture identification information. Stated another way, a frame rate converter, in response to corrupted picture indication information, replaces at least one corrupted source frame with a temporally modified frame created from at least one alternate source frame. The corrupted picture identification information indicates that a source frame, or segment thereof, includes at least one corrupted or dropped source frame (or segment thereof).

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

Abstract: A method includes intra-refresh encoding each picture of a first set of pictures such that a position of a refresh region for the picture is spatially shifted relative to the position of the refresh region for a previous picture of the first set responsive to determining global motion associated with the first does not exceed a specified threshold. The method further includes intra-refresh encoding each picture of a second set of pictures such that a position of a refresh region for each picture of the second set is fixed to be immediately adjacent to a picture edge that is in a direction of global motion associated with the second set responsive to determining the global motion associated with the second set exceeds the specified threshold.

Abstract: A GPU performs dynamic power level management by switching between pre-defined power levels having distinct clock and voltage levels. The dynamic power level management includes identifying a first performance metric associated with processing workloads at the for a consecutive number of measurement cycles. In some embodiments, the consecutive number of measurement cycles includes a current measurement cycle and at least one previous measurement cycle. Based on a determination that the consecutive number of measurement cycles exceeds a minimum hysteresis number, an estimated optimization is determined to be applied to the GPU for a future measurement cycle. A power level setting at the GPU for the future measurement cycle is adjusted based on the estimated optimization. By considering performance metrics including, for example, different processing workloads and hardware configurations, the GPU is able to dynamically adapt its power settings to the particular workload that it is currently processing.