Patents Assigned to ATI
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Patent number: 10094003Abstract: An alpha-beta titanium alloy comprises, in weight percentages: an aluminum equivalency in the range of 2.0 to 10.0; a molybdenum equivalency in the range of 0 to 20.0; 0.3 to 5.0 cobalt; and titanium. In certain embodiments, the alpha-beta titanium alloy exhibits a cold working reduction ductility limit of at least 25%, a yield strength of at least 130 KSI (896.3 MPa), and a percent elongation of at least 10%. A method of forming an article comprising the cobalt-containing alpha-beta titanium alloy comprises cold working the cobalt-containing alpha-beta titanium alloy to at least a 25 percent reduction in cross-sectional area. The cobalt-containing alpha-beta titanium alloy does not exhibit substantial cracking during cold working.Type: GrantFiled: January 12, 2015Date of Patent: October 9, 2018Assignee: ATI PROPERTIES LLCInventor: John W. Foltz, IV
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Patent number: 10095295Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: GrantFiled: December 14, 2011Date of Patent: October 9, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Patent number: 10085017Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.Type: GrantFiled: November 29, 2012Date of Patent: September 25, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Lei Zhang, Ji Zhou, Zhen Chen, Min Yu
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Patent number: 10074600Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.Type: GrantFiled: March 30, 2012Date of Patent: September 11, 2018Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
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Patent number: 10067019Abstract: A force/torque sensor includes a number n of deformable beams connecting the TAP to the MAP, wherein n?4. At least four of the n deformable beams are instrumented with strain gages affixed to surfaces of the beams, such that each beam outputs two gage signals. The eight gage signals are grouped into four sets of six gage signals, such that each set includes the gage signals from three of the four instrumented beams. Each set of six gage signals is multiplied by a calibration matrix to yield a set of six force and torque values. The four sets of force and torque values are compared. If one set disagrees with the other three by greater than a predetermined tolerance, a sensor fault is signaled.Type: GrantFiled: January 9, 2017Date of Patent: September 4, 2018Assignee: ATI Industrial Automation, Inc.Inventors: Everett Lester Bradford, Dwayne Perry
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Publication number: 20180246816Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180246815Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Patent number: 10063834Abstract: A method and apparatus for processing video utilize individually collected image enhancement statistic information from differing processor cores for a same frame or multi-view that are then either shared between the processor cores or used by a third processor core to combine the statistical information that has been individually collected to generate global image-enhancement control information. The global image enhancement control information is based on a global analysis of both left and right eye views for example using the independently generated statistic information for a pair of frames. Respective image output information is produced by each of the plurality of processor cores based on the global image enhancement control information, for display on one or more displays.Type: GrantFiled: September 13, 2011Date of Patent: August 28, 2018Assignee: ATI Technologies ULCInventor: Edward G. Callway
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Patent number: 10056027Abstract: A virtualized DisplayPort (DP) configuration data (DPCD) for multi-stream transport (MST) logical DP end points and non-DP end points allows DPCD configuration for links within a DisplayPort topology which are not configurable using DPCD. A virtualized DPCD may configure a link to an internal display of a MST sink device or a non-DP display to receive data using a dynamic refresh rate (DRR), display stream compression (DSC), panel self-refresh (PSR) and other DPCD configurable features.Type: GrantFiled: November 18, 2016Date of Patent: August 21, 2018Assignee: ATI Technologies ULCInventor: Syed Athar Hussain
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Patent number: 10053758Abstract: Certain embodiments of a method for increasing the strength and toughness of a titanium alloy include plastically deforming a titanium alloy at a temperature in an alpha-beta phase field of the titanium alloy to an equivalent plastic deformation of at least a 25% reduction in area. After plastically deforming the titanium alloy in the alpha-beta phase field, the titanium alloy is not heated to or above the beta transus temperature of the titanium alloy. After plastic deformation, the titanium alloy is heat treated at a heat treatment temperature less than or equal to the beta transus temperature minus 20° F. (11.1° C.).Type: GrantFiled: January 22, 2010Date of Patent: August 21, 2018Assignee: ATI Properties LLCInventor: David J. Bryan
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Patent number: 10055857Abstract: A system, method and computer program product to traverse a polygon mesh, partition the polygon mesh into a set of polygon fans based on the traversal order, and tessellate the set of polygon fans into triangles based on the traversal order. This transformation of the polygon mesh into a triangle mesh enables the polygon mesh to be compressed and decompressed using the SC3DMC standard.Type: GrantFiled: August 29, 2014Date of Patent: August 21, 2018Assignee: ATI Technologies ULCInventor: Khaled Mammou
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Patent number: 10047908Abstract: A robotic tool changer includes a locking feature, and may be made washable by sealing against fluid incursion. The tool changer comprises a master unit and one or more tool units, and it transitions between decoupled and coupled states by rotation of one part relative to another. The rotation displaces rolling members in the master unit, such as balls, from a retaining surface to a locking surface which is sized and positioned to force the rolling members against a coupling surface of the tool unit. A deformable pin interposed between the retaining and locking surfaces resists movement of the rolling members therebetween, requiring the application of force. The pin remains deformed, and continues to exert a force on the rolling members, when the robotic tool changer is in the coupled state, providing a locking feature which automatically and positively resists any inadvertent decoupling of the tool changer.Type: GrantFiled: June 20, 2017Date of Patent: August 14, 2018Assignee: ATI Industrial Automation, Inc.Inventors: David John Bohle, II, Michael Joseph Gala
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Patent number: 10045003Abstract: A method for determining a macroblock (MB) coding mode for a current MB in a dependent view. A window around a co-located MB in a base view is determined, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view. A coding mode complexity value (CMCV) is determined for each MB in the window, wherein the CMCV is based on a coding mode used to encode the MB. Rate distortion optimization (RDO) is performed for the current MB using a reduced number of coding modes if a total CMCV for all MBs in the window is less than a threshold, or using all supported coding modes if the total CMCV for all MBs in the window is greater than the threshold. A coding mode for the current MB is determined based on the RDO results.Type: GrantFiled: April 14, 2016Date of Patent: August 7, 2018Assignee: ATI TECHNOLOGIES ULCInventors: Jiao Wang, Mohamed K. Cherif
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Patent number: 10043481Abstract: A method and device of over training a connection is provided. Noise is intentionally supplied and added to a signal that is subjected to a link training operation. The link training operation is used to obtain a link between a source device and a receiving device. The device includes a noise source from which noise is obtained and added to a signal to aid in link over-training.Type: GrantFiled: May 18, 2015Date of Patent: August 7, 2018Assignee: ATI Technologies ULCInventor: James D. Hunkins
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Publication number: 20180217844Abstract: A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: John Kalamatianos, Greg Sadowski, Syed Zohaib M. Gilani
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Patent number: 10025721Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.Type: GrantFiled: October 24, 2014Date of Patent: July 17, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien, Yaniv Adiri
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Patent number: 10021413Abstract: Methods and apparatus for facilitating processing a reference frame to produce an output frame. Motion vector data for a block of reference frame pels estimates the displacement of the reference frame pels from corresponding pels in a prior input frame. Comparison metrics are produced for a pel of the reference frame with respect to that pel and a plurality of neighboring reference frame pels. A first comparison metric is based on a comparison with corresponding pels of a prior output frame that corresponds to the prior input frame as previously processed. A second comparison metric is based on a comparison with corresponding pels of a motion compensated prior output frame derived from applying motion vector data to the pels of the prior output frame. A pel of the output frame that corresponds to the reference frame pel is determined using the first and second comparison metrics.Type: GrantFiled: December 22, 2016Date of Patent: July 10, 2018Assignee: ATI Technologies ULCInventors: Sahar Alipour Kashi, Boris Ivanovic, Allen J. Porter
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Patent number: 10011885Abstract: A method of producing an article selected from a titanium article and a titanium alloy article comprises melting feed materials with a source of hydrogen to form a molten heat of titanium or a titanium alloy, and casting at least a portion of the molten heat to form a hydrogenated titanium or titanium alloy ingot. The hydrogenated ingot is deformed at an elevated temperature to form a worked article comprising a cross-sectional area smaller than a cross-sectional area of the hydrogenated ingot. The worked article is dehydrogenated to reduce a hydrogen content of the worked article. In certain non-limiting embodiments of the method, the dehydrogenated article comprises an average ?-phase particle size of less than 10 microns in the longest dimension.Type: GrantFiled: February 8, 2016Date of Patent: July 3, 2018Assignee: ATI PROPERTIES LLCInventors: Richard L. Kennedy, Robert M. Davis, Rex W. Bradley, Robin M. Forbes Jones
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Publication number: 20180181488Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Mark Fowler, Jimshed Mirza, Anthony Asaro
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Patent number: RE47054Abstract: A multiplexed packetized data stream carrying real-time multimedia programs is received at a first hardware demultiplexer. Based on a user input, a video and timing portion of a program associated with the multiplexed packetized data stream can be stored for subsequent display. One type of subsequent display is time shifted display, where the stored portion of the program is played back while new portions of the program are being stored. During time shifted play back, a second hardware demultiplexer can be used, so that one demultiplexer stores new data and maintains a current clock value while the other decodes and displays the stored data.Type: GrantFiled: December 2, 2016Date of Patent: September 18, 2018Assignee: ATI Technologies ULCInventor: Branko Kovacevic