Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Systems, methods and apparatuses of processing data of a VR system are disclosed that comprise receiving tracking information which includes at least one of user position information and eye gaze point information. One or more processors may be used to predict, based on the user tracking information, a user viewpoint of a next frame of a sequence of frames of video data to be displayed. Using the prediction, a portion of the next frame of video data to be displayed is rendered at an estimated location in the next frame. A corresponding matching portion in a previously encoded frame is determined based on the estimated location of the portion in the next frame and the portion of the next frame of video data is encoded.

Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.

Abstract: A method of processing a non-magnetic alloy workpiece comprises heating the workpiece to a warm working temperature, open die press forging the workpiece to impart a desired strain in a central region of the workpiece, and radial forging the workpiece to impart a desired strain in a surface region of the workpiece. In a non-limiting embodiment, after the steps of open die press forging and radial forging, the strain imparted in the surface region is substantially equivalent to the strain imparted in the central region. In another non-limiting embodiment, the strain imparted in the central and surface regions are in a range from 0.3 inch/inch to 1 inch/inch, and there exists no more than a 0.5 inch/inch difference in strain of the central region compared with the strain of the surface region of the workpiece. An alloy forging processed according to methods described herein also is disclosed.

Abstract: A robotic tool changer in which the coupling mechanism is actuated using magnetic force is provided. In one exemplary embodiment, a robotic tool changer may include a tool unit operatively connected to a robotic tool and a master unit operative to connect to a robotic arm. The master unit may include a housing and a piston. The piston may be disposed at least partially within the housing and configured to place the master unit in one of a coupled state and a decoupled state. Further, the master unit may be operative to assume the coupled state or the decoupled state in response to altering an orientation of magnetic fields to provide a first magnetic force that moves the piston to the coupled state or provide a second magnetic force that moves the piston to the decoupled state.

Abstract: An encoder encodes pixels representative of a picture in a multimedia stream, generates a first approximate signature based on approximate values of pixels in a reconstructed copy of the picture, and transmits the encoded pixels and the first approximate signature. A decoder receives a first packet including the encoded pixels and the first approximate signature, decodes the encoded pixels, and transmits a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels. If a corrupted packet is detected, the multimedia application requests an intra-coded picture in response to the first approximate signature differing from the second approximate signature. The second signal instructs the decoder to bypass requesting an intra-coded picture and to continue decoding received packets in response to the first approximate signature being equal to the second approximate signature.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: An austenitic stainless steel composition having low nickel and molybdenum and exhibiting high corrosion resistance and good formability. The austenitic stainless steel includes, in weight %, up to 0.20 C, 2.0-6.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 5.0-7.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.1-0.35 N, up to 4.0 W, up to 0.01 B, up to 1.0 Co, iron and impurities. The austenitic stainless steel has a ferrite number less than 11 and an MD30 value less than ?10° C.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.

Abstract: In a processing system including a plurality of graphics processing units (GPUs), the GPUs transfer compressed graphics streams composed of blocks of graphics data to one another. Some blocks of a compressed graphics stream, or parts thereof, may contain both compressed graphics data and meaningless data (referred to as data structure padding, or padding) that is used to align the graphics data, and some blocks may contain only padding. Before transferring a compressed graphics resource from one GPU to another GPU, the sending GPU compacts the compressed graphics resource by filtering out padding from the compressed graphics stream prepared for the transfer.

Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

Abstract: A texture decompression method is described. The method comprises receiving a compressed texture block, determining a partition of pixels used for the compressed texture block, wherein the partition includes one or more disjoint subsets into which data in the compressed texture block is to be unpacked, unpacking data for each subset based on the determined partition, and decompressing each of the one or more disjoint subsets to form an approximation of an original texture block.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.

Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.

Abstract: Systems, apparatuses, and methods for compressing pixel data are disclosed. In one embodiment, if a block of pixel data is equal to a constant value, a processor compresses the block down to a metadata value which specifies the constant value for the entire block of pixel data. The processor also detects if the constant value is equal to a video specific typical minimum or maximum value. In another embodiment, the processor receives a plurality of M-bit pixel components which are most significant bit aligned in N-bit containers. Next, the processor shifts the M-bit pixel components down into least significant bit locations of the N-bit containers. Then, the processor converts the N-bit containers into M-bit containers. Next, the processor compresses the M-bit containers to create a compressed block of pixel data which is then stored in a memory subsystem.

Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.

Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.

Abstract: An alloy is disclosed comprising up to 0.05 weight percent carbon, 27.0 to 31.0 weight percent chromium, up to 0.5 weight percent copper, 7.0 to 11.0 weight percent iron, up to 0.5 weight percent manganese, up to 0.015 weight percent sulfur, up to 0.5 weight percent silicon, at least 58 weight percent nickel, and incidental impurities, wherein the alloy exhibits an ASTM grain size of 3.0 to 9.0, exhibits a uniform grain size distribution, includes intergranular M23C6 carbide precipitates uniformly distributed on grain boundaries, and includes minimal or no intragranular M23C6 carbide precipitates. Articles of manufacture including the alloy also are described.