Patents Assigned to ATI
  • Patent number: 10291931
    Abstract: Techniques are provided for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 14, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Mehdi Saeedi
  • Patent number: 10272487
    Abstract: A system and method for continuous casting. The system includes a melt chamber, a withdrawal chamber, and a secondary chamber therebetween. The melt chamber can maintain a melting pressure and the withdrawal chamber can attain atmospheric pressure. The secondary chamber can include regions that can be adjusted to different pressures. During continuous casting operations, the first region adjacent to the melt chamber can be adjusted to a pressure that is at least slightly greater than the melting pressure; the pressure in subsequent regions can be sequentially decreased and then sequentially increased. The pressure in the final region can be at least slightly greater than atmospheric pressure. The differential pressures can form a dynamic airlock between the melt chamber and the withdrawal chamber, which can prevent infiltration of the melt chamber by non-inert gas in the atmosphere, and thus can prevent contamination of reactive materials in the melt chamber.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 30, 2019
    Assignee: ATI PROPERTIES LLC
    Inventor: Matthew J. Arnold
  • Publication number: 20190122417
    Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
    Type: Application
    Filed: November 2, 2018
    Publication date: April 25, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 10268620
    Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 23, 2019
    Assignee: ATI Technologies ULC
    Inventor: Nima Osqueizadeh
  • Patent number: 10260120
    Abstract: A process for reducing flatness deviations in an alloy article is disclosed. An alloy article may be heated to a first temperature at least as great as a martensitic transformation start temperature of the alloy. A mechanical force may be applied to the alloy article at the first temperature. The mechanical force may tend to inhibit flatness deviations of a surface of the alloy article. The alloy article may be cooled to a second temperature no greater than a martensitic transformation finish temperature of the alloy. The mechanical force may be maintained on the alloy article during at least a portion of the cooling of the alloy article from the first temperature to the second temperature.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 16, 2019
    Assignee: ATI PROPERTIES LLC
    Inventors: Glenn J. Swiatek, Ronald E. Bailey
  • Patent number: 10252327
    Abstract: Various enhanced features are provided for centrifugal casting apparatuses, rotatable assemblies, and molds for casting products from molten material. These enhanced features include, among others, tapered gate portions positioned adjacent to the cavities of a mold, extended and shared gating systems, and detachable mold structures for modifying the thermodynamic characteristics and behavior of molds during casting operations.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: April 9, 2019
    Assignee: ATI PROPERTIES LLC
    Inventors: John W. Foltz, IV, Raul A. Martinez-Ayers, Aaron L. Fosdick
  • Patent number: 10250909
    Abstract: A processing device for use with a video conferencing network is provided. The processing device includes memory configured to store data and a processor. The processor is configured to determine a first sampling phase for a portion of first video data and chrominance sub-sample the portion of first video data using the first sampling phase. The processor is also configured to encode the sub-sampled portion of first video data and decode a sub-sampled, encoded portion of second video data. The processor is further configured to determine a second sampling phase at which the portion of second video data is chrominance sub-sampled and chrominance up-sample the portion of second video data using the second sample phase.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 2, 2019
    Assignee: ATI Technologies ULC
    Inventors: Boris Ivanovic, Allen J. Porter
  • Patent number: 10242647
    Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventor: Yuxin Chen
  • Patent number: 10241925
    Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 26, 2019
    Assignee: ATI Technologies ULC
    Inventors: Jimshed Mirza, Anthony Chan, Edwin Chi Yeung Pang
  • Patent number: 10243727
    Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 26, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Winthrop Wu, James Goodman, Martin Kiernicki, Yoichi Shimokawa, William Thomas Morrison, Creighton Eldridge, David Kaplan
  • Patent number: 10232434
    Abstract: An apparatus for casting metals by a nucleated casting technique to create a preform, the apparatus including a mold having a base and a side wall where the base can be moved relative to the side wall to withdraw the preform as it is being created. In various circumstances, portions of a droplet spray created by an atomizing nozzle, i.e., overspray, may accumulate on a top surface of the side wall and prevent or inhibit the preform from being moved relative to the side wall. The atomizing nozzle can be oriented such that the droplet spray passes over the top of the side wall to remelt and remove at least a portion of the overspray that has accumulated thereon. The mold can be rotated such that the overspray formed on a region of or on the entire perimeter of the top surface can pass through the droplet spray and can be removed from the side wall.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: March 19, 2019
    Assignee: ATI PROPERTIES LLC
    Inventors: Robin M. Forbes Jones, Sterry A. Shaffer
  • Patent number: 10230370
    Abstract: In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 12, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Mark Edward Frankovich
  • Patent number: 10223280
    Abstract: A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 5, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Vydhyanathan Kalyanasundharam, Yaniv Adiri, Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien
  • Patent number: 10218273
    Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Erhan Ergin, Dipanjan Sengupta, Elsie Lo, Stephen V. Kosonocky, Sree Rajesh Saha, Divya Guruja
  • Publication number: 20190056958
    Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Brian K. Bennett
  • Patent number: 10207312
    Abstract: Forge lubrication processes are disclosed. A solid lubricant sheet is placed between a workpiece and a die in a forging apparatus. Force is applied to the workpiece with the die to plastically deform the workpiece. The solid lubricant sheet decreases the shear factor for the forging system and reduces the incidence of die-locking.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: February 19, 2019
    Assignee: ATI PROPERTIES LLC
    Inventors: Scott Oppenheimer, Robin M. Forbes Jones, John Mantione, Ramesh Minisandram, Jean-Philippe Thomas
  • Patent number: 10210845
    Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 19, 2019
    Assignee: ATI Technologies ULC
    Inventors: David I. J. Glen, Syed A. Hussain
  • Patent number: 10209991
    Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: February 19, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Meenakshi Sundaram Bhaskaran, Elliot H. Mednick, David A. Roberts, Anthony Asaro, Amin Farmahini-Farahani
  • Patent number: 10205956
    Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 12, 2019
    Assignee: ATI Technologies ULC
    Inventors: Konstantine Iourcha, Andrew S. C. Pomianowski
  • Patent number: 10198283
    Abstract: A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 5, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices (Shanghai) Co., LTD.
    Inventors: Jeffrey G. Cheng, Yinan Jiang, Guangwen Yang, Kelly Donald Clark Zytaruk, LingFei Liu, XiaoWei Wang