Abstract: A thermo-mechanical treatment process is disclosed. A nickel-base alloy workpiece is heated in a first heating step to a temperature greater than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is worked in a first working step to a reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than the M23C6 carbide solvus temperature when the first working step begins. The nickel-base alloy workpiece is heated in a second working step to a temperature greater than 1700° F. (926° C.) and less than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is not permitted to cool to ambient temperature between completion of the first working step and the beginning of the second heating step. The nickel-base alloy workpiece is worked to a second reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than 1700° F. (926° C.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: A method and apparatus are described for performing video encoding mode decisions in a video transcoding system. A down-scaled frame may be received that includes at least one macroblock. The down-scaled frame may be associated with a full-scale frame having a plurality of macroblocks that have been downsampled. A weighting factor and a distance measure factor may be determined for each of the macroblocks in the full-scale frame. Predicted blocks may be generated based on the weighting and distance measure factors.

Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.

Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.

Abstract: Methods and apparatus for facilitating processing a reference frame to produce an output frame. Motion vector data for a block of reference frame pels estimates the displacement of the reference frame pels from corresponding pels in a prior input frame. Comparison metrics are produced for a pel of the reference frame with respect to that pel and a plurality of neighboring reference frame pels A first comparison metric is based on a comparison with corresponding pels of a prior output frame that corresponds to the prior input frame as previously processed. A second comparison metric is based on a comparison with corresponding pels of a motion compensated prior output frame derived from applying motion vector data to the pels of the prior output frame. A pel of the output frame that corresponds to the reference frame pel is determined using the first and second comparison metrics.

Abstract: One aspect of the present disclosure is directed to a metastable ? titanium alloy comprising, in weight percentages: up to 0.05 nitrogen; up to 0.10 carbon; up to 0.015 hydrogen; up to 0.10 iron; greater than 0.20 oxygen; 14.00 to 16.00 molybdenum; titanium; and incidental impurities. Articles of manufacture including the alloy also are disclosed.

Abstract: The present disclosure relates to a method and apparatus for electronic device communication. A method includes translating monitor control commands to an internet protocol (IP) format to produce IP formatted monitor control commands, and communicating the IP formatted monitor control commands to an IP port dedicated for communicating IP formatted monitor control commands.

Abstract: An aspect of the present disclosure is directed to low-alloy steels exhibiting high hardness and an advantageous level of multi-hit ballistic resistance with low or no crack propagation imparting a level of ballistic performance suitable for military armor applications. Various embodiments of the steels according to the present disclosure have hardness in excess of 550 BHN and demonstrate a high level of ballistic penetration resistance relative to conventional military specifications.

Abstract: A virtualized DisplayPort (DP) configuration data (DPCD) for multi-stream transport (MST) logical DP end points and non-DP end points allows DPCD configuration for links within a DisplayPort topology which are not configurable using DPCD. A virtualized DPCD may configure a link to an internal display of a MST sink device or a non-DP display to receive data using a dynamic refresh rate (DRR), display stream compression (DSC), panel self-refresh (PSR) and other DPCD configurable features.

Abstract: A translation layer includes a plurality of first buffers and a controller to assert one or more ready signals corresponding to one or more of the plurality of first buffers in response to the one or more of the plurality of first buffers being less than full. The one or more of the plurality of first buffers receives data or control information from one or more corresponding components in response to the ready signal being asserted concurrently with one or more valid signals asserted by the one or more corresponding components.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: A method of reducing the formation of electrically resistive scale on a an article comprising a silicon-containing ferritic stainless subjected to oxidizing conditions in service includes, prior to placing the article in service, subjecting the article to conditions under which silica, which includes silicon derived from the steel, forms on a surface of the steel. Optionally, at least a portion of the silica is removed from the surface to placing the article in service. A ferritic stainless steel alloy having a reduced tendency to form silica on at least a surface thereof also is provided. The steel includes a near-surface region that has been depleted of silicon relative to a remainder of the steel.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: A vehicle track module having a frame, the module mountable on a rotatable axle of a vehicle and having a drive wheel rotatably mounted to the frame, leading and trailing idler wheels rotatably mounted to the frame, at least one bogie wheel in contact with the track and positioned between the idler wheels, and a continuous flexible track extending about the wheels, and the at least one bogie wheel is a cylindrical wheel with a tapered elastomeric tire therearound. The track module may include a module center plane parallel to the drive wheel and the bogie wheel may be thicker toward the center plane. A track assembly for a vehicle including a frame for mounting with respect to the vehicle and a plurality of wheels in contact with a continuous flexible track extending about the wheels with at least one wheel being cylindrical and including a tapered elastomeric tire.

Abstract: A method, a device, and a non-transitory computer readable medium for performing dithering on an L bit long input data are presented. An M bit long random data is generated, wherein M is a number of least significant bits of the input data. An M bit long frame counter value is added to the random data. The input data is rounded up to L-M most significant bits when the M least significant bits of the input data is greater than the sum of the frame counter value and the random data. The input data is truncated to the L-M most significant bits when the M least significant bits of the input data is less than or equal to the sum of the frame counter value and the random data.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

Abstract: A method of producing a seamless, composite tubular product includes centrifugally casting a metal or alloy into a tubular workpiece having an inner diameter. The method then centrifugally casts a corrosion resistant alloy in the inner diameter of the tubular workpiece to form a composite tubular workpiece having an inner diameter and an outer diameter. The inner diameter of the composite tubular workpiece is formed of the corrosion resistant alloy, and the outer diameter is formed of the metal or alloy. The method then subjects the composite tubular workpiece to at least about a 25% wall reduction at a temperature below a recrystallization temperature of the workpiece using a metal forming process. The metal forming process includes radial forging, rolling, pilgering, and/or flowforming.

Abstract: Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of “hardware memory mover” does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth.

Abstract: A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.