Abstract: In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

Abstract: An apparatus for melting an electrically conductive metallic material includes a vacuum chamber and a hearth disposed in the vacuum chamber. At least one wire-discharge ion plasma electron emitter is disposed in or adjacent the vacuum chamber and is positioned to direct a wide-area field of electrons into the vacuum chamber, wherein the wide-area electron field has sufficient energy to heat the electrically conductive metallic material to its melting temperature. The apparatus may further include at least one of a mold and an atomizing apparatus which is in communication with the vacuum chamber and is positioned to receive molten material from the hearth.

Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.

Abstract: Graphics rendering settings in a computer system are adjusted when an activity level on a bus meets a trigger condition. The graphics rendering settings of the system are returned to a previous level when the bus activity drops below a threshold. The trigger condition may be related to bandwidth usage on the bus or latency of data sent over the bus.

Abstract: Processes for producing a nickel-titanium alloy are disclosed. The processes are characterized by the production of nickel-titanium alloy articles having improved microstructure. A pre-alloyed nickel-titanium alloy is melted and atomized to form molten nickel-titanium alloy particles. The molten nickel-titanium alloy particles are cooled to form nickel-titanium alloy powder. The nickel-titanium alloy powder is consolidated to form a fully-densified nickel-titanium alloy preform that is hot worked to form a nickel-titanium alloy article. Any second phases present in the nickel-titanium alloy article have a mean size of less than 10 micrometers measured according to ASTM E1245-03 (2008) or an equivalent method.

Abstract: Apparatus include(s) a package having a load, and methods of making an electronic circuit include disposing the package on a printed circuit board. The apparatus include(s) an integrated conducting element and inductive element disposed on the printed circuit board and connected to the package that includes the load. The methods include disposing the integrated conducting element and inductive element on the printed circuit board so that the integrated conducting element and inductive element connects to the package. The integrated conducting element and inductive element includes a conducting element integral with an inductive element. The inductive element includes a magnetic element and a winding element. The winding element comprises a portion of the conducting element.

Abstract: A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. A system for implementing the method and a non-transitory computer-readable storage medium for storing instructions of the method are also disclosed.

Abstract: Track-module bogie-suspension apparatus for attachment to a track module having a frame, a drive wheel and an endless track. The bogie-suspension apparatus comprises (a) a bogie assembly having a bogie mount, at least one rotatable ground-engaging bogie wheel thereon, and forward and rearward bogie-mount connections; (b) first and second load- and ground-responsive suspension joints spaced from one another in a forward/rearward direction; and (c) leading and trailing suspension elements each having an upper end and a lower end, the upper ends of the leading and trailing suspension elements rotatably attached to the first and second suspension joints, respectively, and the lower ends thereof rotatably attached to the rearward and forward bogie-mount connections, respectively.

Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: Methods and apparatus for facilitating motion estimation in video processing are provided. In one embodiment, search block is defined within one frame. A relative location of a corresponding block in another frame with respect to the search block is determined based on comparative searching at a predetermined granularity to produce a motion vector for the search block with a first precision. Correlation values are determined with respect to the search block for the corresponding block and for one block or more blocks defined at relative locations of less than the predetermined granularity with respect to the corresponding block in different directions. A refined motion vector for the search block with a second higher precision is determined based on the relative location of the block having a selected correlation value that is selected from among the determined correlation values.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: Track-module bogie-suspension apparatus for attachment to a track module having a frame, a drive wheel and an endless track. The bogie-suspension apparatus comprises (a) a bogie assembly having a bogie mount, at least one rotatable ground-engaging bogie wheel thereon, and forward and rearward bogie-mount connections; (b) first and second load- and ground-responsive suspension joints spaced from one another in a forward/rearward direction; and (c) leading and trailing suspension elements each having an upper end and a lower end, the upper ends of the leading and trailing suspension elements rotatably attached to the first and second suspension joints, respectively, and the lower ends thereof rotatably attached to the rearward and forward bogie-mount connections, respectively.

Abstract: In vehicle track-module apparatus including a module frame, a drive wheel rotatable with respect to the frame, ground-engaging leading and trailing wheels, at least one ground-engaging bogie wheel, and an endless track extending around the wheels and driven by its engagement with the drive wheel, the improvement comprising: (a) a leading suspension arm rotatable with respect to the frame and extending forwardly to a distal end at which a leading-wheel assembly is rotatably attached and rearwardly to a rearward suspension end; (b) a trailing suspension arm rotatable with respect to the frame and extending rearwardly to a distal end at which a trailing-wheel assembly is rotatably attached and forwardly to a forward suspension end; (c) a bogie assembly having a bogie mount and the at least one bogie wheel rotatable with respect thereto; and (d) leading and trailing suspension elements rotatably attached to and extending from the rearward and forward suspension ends, respectively, to rearward and forward rotatabl

Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.

Abstract: In vehicle track-module apparatus including a module frame, a drive wheel rotatable with respect to the frame, ground-engaging leading and trailing wheels, at least one ground-engaging bogie wheel, and an endless track extending around the wheels and driven by its engagement with the drive wheel, the improvement comprising: (a) a leading suspension arm rotatable with respect to the frame and extending forwardly to a distal end at which a leading-wheel assembly is rotatably attached and rearwardly to a rearward suspension end; (b) a trailing suspension arm rotatable with respect to the frame and extending rearwardly to a distal end at which a trailing-wheel assembly is rotatably attached and forwardly to a forward suspension end; (c) a bogie assembly having a bogie mount and the at least one bogie wheel rotatable with respect thereto; and (d) leading and trailing suspension elements rotatably attached to and extending from the rearward and forward suspension ends, respectively, to rearward and forward rotatabl

Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.

Abstract: A method and apparatus to maximize video slice size is described herein. The method packs as many macroblocks as possible within a capped-size slice, while preserving user-defined quality constraints. The probability to conform to the maximum slice size constraint may be adjusted according to a user-defined parameter. The method may be integrated into a rate control process of a video encoder. The method predicts whether encoding a macroblock with a quantization parameter exceeds a current slice size constraint. It further predicts whether encoding a given number of macroblocks with a given configuration of quantization parameters exceeds the current slice size constraint. The method then proceeds to encode the current macroblock either on a condition that encoding the given number of macroblocks with the given configuration of quantization parameters falls below the size constraint of the current slice or after determining that a new slice is needed.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: Methods and apparatus that allow encoding of video data in pipelined encoder architectures with reduced encoding performance penalty. The methods and apparatus encode video data without the need to flush the data pipeline and re-encode macroblocks, thus saving time and resulting in an increase in the encoder's throughput. In one embodiment, macroblocks are encoded in a data pipeline to form a first video slice of a plurality of video slices. Once a macroblock overshoot condition occurs, the overshooting macroblock is determined and a second video slice is formed that includes at least one of the overshooting macroblock and the encoded macroblocks without re-encoding the included overshooting macroblock and encoded macroblocks. For example, a second video slice may be formed from the overshooting macroblock, and any remaining encoded macroblocks, that do not form the first video slice.