Abstract: Discloses herein are methods, apparatuses, and systems for preparing and displaying images in frame-sequential stereoscopic 3D. Frame-sequential stereoscopic display includes an alternating sequence of left- and right-perspective images for display. Disclosed methods include identifying pixels that modulate due to the alternating sequence of left- and right-perspective images of the frame-sequential stereoscopic display. The disclosed methods also include processing the pixels to reduce one or more residual images caused by the alternating sequence of left- and right-perspective images of the frame-sequential stereoscopic display. The disclosed methods may be implemented by a processing unit and the processing unit may be included in a system (such as, a computer or video-game console).

Abstract: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.

Abstract: The present disclosure relates to methods and apparatus for detecting text information in a video signal that includes subtitles, captions, credits, or other text, and also for applying enhancements to the display of text areas in video. The sharpness and/or contrast ratio of subtitles of detected text areas may be improved. Text areas may be displayed in a magnified form in a separate window on a display, or on a secondary display. Further disclosed are methods and apparatus for extending the duration for which subtitles appear on the display, for organizing subtitles to be displayed in a scrolling format, for allowing the user to control when a subtitle advances to the next subtitle using a remote control, and for allowing a user to scroll back to a past subtitle in cases where the user has not finished reading a subtitle.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: The present invention provides a scheme for compressing the color components of image data, and in particular, data used in multi-sampled anti-aliasing applications. Adjacent pixels are grouped into rectangular tiles, with the sample colors stored in compressed formats accessible via an encoded pointer. In one embodiment, duplicate colors are stored once. Unlike prior compression schemes that rely on pixel to pixel correlation, the present invention takes advantages of the sample to sample correlation that exists within the pixels. A memory and graphics processor configuration incorporating the tile compression schemes is also provided. The configuration defines the tile sizes in main memory and cache memory. In one embodiment, graphics processor relies on a Tile Format Table (TFT) to process incoming tiles in compressed formats. The present invention reduces memory consumption and speeds up essential and oft-repeated operations in rendering.

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: An adjustable cheek rest assembly for a firearm includes a stock adapted to be mounted on a support member of the firearm, and a cheek rest disposed in overlying relationship to the stock. A cheek rest adjustment arrangement is connected between the stock and the cheek rest and includes a movable linkage for enabling adjustment of the cheek rest relative to the stock.

Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.

Abstract: A method and apparatus for transcoding video data decodes video that is encoded in the first format and produces decoded data blocks that include decoded tile data such that each decoded block includes pixel data for multiple display lines. The method and apparatus performs a linear write operation on the decoded data block by controlling storing of the decoded data block rows in consecutive linear addresses in memory such that one line of memory comprises decoded data for multiple display lines from the same block. The method and apparatus fetches the line of memory and re-encodes the data into a data block format, In one example translation of the fetched line of memory back into the original decoded data block format is performed for re-encoding such that the block of data includes data for multiple display lines. The video data is re-encoded to the second format using the decoded data block that was translated from the fetched line of memory.

Abstract: A system and method for providing viewer preferences on a display device are presented. An embodiment includes a storage medium for storing preset viewer preferences, each preference being categorized based on one of a plurality of viewers, a processor that accesses the storage medium and acquires the stored preset viewer preference for a given one of the plurality of viewers, and a display device that provides content to the viewer in accordance with the viewer's preferences using at least one optical element.

Abstract: One or more specialized field programmable modules (e.g. CPLD and FPGA blocks) and their programming interface are embedded into a processing system (e.g. a CPU, GPU, APU and/or chipset). The field programmable modules are in-system programmable, in contrast to the application specific integrated circuit (ASIC) modules that perform the core functions of the processing system. The programmable flexibility of the field programmable modules can have various benefits during different stages of the integrated circuit life cycle for the processing system, such as reconfigurable interface bridging and two-way I/O expansion.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: The invention described herein includes a system, method, and computer program product for adding functionality to an application program. The invention includes a tool which can be used in conjunction with any of a plurality of application programs. The tool can be represented to a user by a tool icon on a desktop. After creating or opening a file or other object with an application program, the user can drag and drop a tool icon representing the tool into the application window. This allows the tool program to operate on the object. A windowing system event handler receives information from a user interface regarding the dragging and dropping of the tool icon. The fact that the tool icon has been dragged and dropped into the application window is reported by the windowing system event handler to a base module. The base module mediates communication between the tool program and the application program.

Abstract: A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

Abstract: Processes and methods related to producing, processing, and hot working alloy ingots are disclosed. An alloy ingot is formed including an inner ingot core and an outer layer metallurgically bonded to the inner ingot core. The processes and methods are characterized by a reduction in the incidence of surface cracking of the alloy ingot during hot working.

Abstract: A scalable high throughput video encoder is described herein. A plurality of dedicated, hardware video encoders runs in a staggered, parallel architecture, where each video encoder encodes a video frame and the stagger or delay is a programmable number of macroblock rows. In an example method, after a first video encoder finishes encoding the first x macroblock rows of a frame, the first video encoder signals a second video encoder to start encoding a macroblock row of a next unprocessed frame. Both video encoders continue encoding in parallel in a synchronized, staggered manner. At the end of the frame, the first video encoder starts encoding x macroblock rows of another unprocessed frame.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.