Abstract: A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels.

Abstract: Processes, systems, and apparatuses are disclosed for forming products from atomized metals and alloys. A stream of molten alloy and/or a series of droplets of molten alloy are produced. The molten alloy is atomized to produce electrically-charged particles of the molten alloy by impinging electrons on the stream of molten alloy and/or the series of droplets of molten alloy. The electrically-charged molten alloy particles are accelerated with at least one of an electrostatic field and an electromagnetic field. The accelerating molten alloy particles are cooled to a temperature that is less than a solidus temperature of the molten alloy particles so that the molten alloy particles solidify while accelerating. The solid alloy particles are impacted onto a substrate and the impacting particles deform and metallurgically bond to the substrate to produce a solid alloy preform.

Abstract: An apparatus for melting an electrically conductive metallic material comprises an auxiliary ion plasma electron emitter configured to produce a focused electron field including a cross-sectional profile having a first shape. The apparatus further comprises a steering system configured to direct the focused electron field to impinge the focused electron field on at least a portion of the electrically conductive metallic material to at least one of melt or heat any solidified portions of the electrically conductive metallic material, any solid condensate within the electrically conductive metallic material, and/or regions of a solidifying ingot.

Abstract: A vehicle track-module including an upper drive wheel, a plurality of idler and bogey wheels, and an endless rubber track with spaced lugs which extends around the wheels and is driven by the drive wheel, which has: a middle main plate with a outer edge of first diameter and inward and outward sides forming the exposed inward and outward surfaces of the drive wheel; drive members axially across and projecting radially beyond the main-plate edge to a second diameter, each drive member having axially inward and outward end portions, a middle portion affixed at its middle position to the main-plate edge, and an outer track-engaging surface; and a rigidity ring affixed to the inward end portions of the drive members and having an inner diameter no less than half the first diameter and an outer diameter no greater than the second diameter. In some embodiments, the axial dimension of the track-engaging surfaces of the drive members is at least 50% greater than the axial dimension of the track lugs.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A robotic tool changer removably attaches a robotic tool to a robotic arm. The changer includes a tool module connected to the robotic tool, and a master module connected to the robotic arm. To attach and detach the robotic tool, the changer couples and uncouples the tool module and the master module. A master electrical signal module (ESM) affixes to the master module and a tool ESM affixes to the tool module. In accordance with design requirements, the changer applies the same power supply to both the master ESM and the tool ESM. The changer, however, selectively suppresses application of the power supply to the tool ESM, while maintaining application of the power supply to the master ESM, during the coupling or uncoupling of the master module and the tool module. In doing so, the changer enables such coupling and uncoupling, while also preventing the formation of transient electric arcs.

Abstract: A method and system of testing pixels output from a pixel generation unit under test includes generating pixels from the pixel generation unit under test using a first test data pattern to generate pixel information. The method and system also generate a per pixel error value for a pixel from the unit under test that contains an error based on the pixel by pixel comparison with pixel information generated substantially concurrently with pixels by a different unit using the first test data pattern. If desired, corresponding pixel screen location information (e.g., x-y location) can also be determined for the pixel that has the error. The per pixel error and x-y location information can be displayed.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: Methods and apparatus for dynamically adjusting a power level of an electronic device (100) are disclosed. In an embodiment, an electronic device (100) receives a usage pattern of the electronic device (100) (e.g., typically used 9:00 AM to 5:00 PM on weekdays). The electronic device (100) then dynamically adjusts a wake up timer (204) associated with the electronic device (100) based on the usage pattern (e.g., expire at 8:50 am the next morning, which is 10 minutes before usage typically resumes for that day). In response to an expiration of the dynamically adjusted wake up timer (204), the electronic device (100) increases the power level of the electronic device (100) (e.g., transition from hibernate mode to standby mode, possibly via other intervening power modes, for faster startup in anticipation of resumed usage).

Abstract: A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

Abstract: A reference voltage generator is provided. In an example, the reference voltage generator includes a temperature-dependent device, a processing module configured to process a digital representations of first and second voltages derived from the temperature-dependent device and a reference voltage to determine a value, and a digital to analog converter (DAC) configured to generate a reference voltage based on the value. The first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute temperature (CTAT) and the reference voltage is substantially independent of absolute temperature in an operating temperature range of the reference voltage generator.

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A charging system having a charging device with a groove for receiving a mobile/portable device for charging is provided having a magnetic core located in a housing of the charging device with the magnetic core having a base and two legs that are located around the groove. A coil is wrapped around the base and a driver circuit is connected to the coil as well as to an external power source. A power receiver is located in a mobile/portable device that can be placed in the groove in the charging device. The power receiver includes a receiver magnetic core as well as a receiving coil wrapped around the receiver magnetic core for receiving an inductive current from the charging device. A charging circuit is connected to the receiving coil and adapted to be connected to the battery of the mobile/portable device for charging.

Abstract: A device receives a request to use a software program, determines a comparison indicator based on receiving the request, and determines whether a license for the software program is valid based on a license validity indicator, stored in a secure environment, and the comparison indicator. The device permits execution of secure code stored in the secure environment when the license is determined to be valid, and prevents execution of the secure code stored in the secure environment when the license is determined to be invalid.

Abstract: A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space.

Abstract: A method and apparatus for correcting a rotation of a video frame are described. According to a method, an amount of the rotation of the video frame with respect to a reference is determined. The rotation of the video frame is corrected based at least in part on the detected amount of the rotation of the video frame.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: Methods for producing alloy strips that demonstrate improved formability are disclosed. The strips have a crystalline microstructure suitable for improved formability in the manufacture of various articles such as panels for plate heat exchangers and high performance tower packing components.

Abstract: Level shifting circuitry and corresponding enable signal generating circuitry provides improved leakage current control while eliminating the need for supplying reference voltage input in the enable signal generator. The level shifting circuitry is a type of cascode free level shifting circuit that does not include cascode transistors as in the prior art but instead utilizes cross coupled logic to provide level shifting while also utilizing enable signal controlled transistors to control leakage current through the cross coupled logic during power up sequencing. The level shifting circuitry provides improved leakage current limiting structure for power up sequencing whether a lower level supply voltage ramps up faster than the higher level supply voltage or vice a versa.