Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.

Abstract: The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: An apparatus and method provides temporal image processing by producing, for output on a single link such as a single cable or wireless interface, packet based multi-steam information wherein one stream provides at least frame N information for temporal imaging processing and a second stream that provides frame N?1 information for the same display, such as a current frame and a previous frame or a current frame and next frame. The method and apparatus also outputs the packet based multi-stream information and sends it for the same display for use by the same display so that the receiving display may perform temporal image processing using the multi-stream multi-frame information sent with a single link.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: Various embodiments relate to interconnects for solid oxide fuel cells (“SOFCs”) comprising ferritic stainless steel and having at least one via that when subjected to an oxidizing atmosphere at an elevated temperature develops a scale comprising a manganese-chromate spinel on at least a portion of a surface thereof, and at least one gas flow channel that when subjected to an oxidizing atmosphere at an elevated temperature develops an aluminum-rich oxide scale on at least a portion of a surface thereof. Other embodiments relate to interconnects comprising a ferritic stainless steel and having a fuel side comprising metallic material that resists oxidation during operation of the SOFCs, and optionally include a nickel-base superalloy on the oxidant side thereof. Still other embodiments relate to ferritic stainless steels adapted for use as interconnects comprising ?0.1 weight percent aluminum and/or silicon, and >1 up to 2 weight percent manganese. Methods of making interconnects are also disclosed.

Abstract: Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory.

Abstract: An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

Abstract: A nucleated casting apparatus including an atomizing nozzle configured to produce a droplet spray of a metallic material, a mold configured to receive the droplet spray and form a preform therein, and a gas injector which can limit, and possibly prevent, overspray from accumulating on the mold. The gas injector can be configured to produce a gas flow which can impinge on the droplet spray to redirect at least a portion of the droplet spray away from a side wall of the mold. In various embodiments, the droplet spray may be directed by the atomizing nozzle in a generally downward direction and the gas flow may be directed in a generally upward direction such that the gas flow circumscribes the perimeter of the mold.

Abstract: An efficient method of compositing planes onto a target surface using a computing device with graphics processing capability is disclosed. The method includes partitioning the target surface, on which planes are composited, into partitions. Each one of the partitions contains connected pixels to be formed by compositing an identical subset of the planes to be composited. Each partition is associated with a corresponding subset of the planes. Each partition and its corresponding set of associated planes are then provided to a graphics processor for composition, using exemplary software components including an application programming interface, a library and device driver software. An image is formed on the target surface by compositing each partition. Using the disclosed method, a single pass through stages of the graphics pipeline for the graphics processor is sufficient to composite multiple planes to form an image on the target surface.

Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.

Abstract: Various embodiments relate to interconnects for solid oxide fuel cells (“SOFCs”) comprising ferritic stainless steel and having at least one via that when subjected to an oxidizing atmosphere at an elevated temperature develops a scale comprising a manganese-chromate spinel on at least a portion of a surface thereof, and at least one gas flow channel that when subjected to an oxidizing atmosphere at an elevated temperature develops an aluminum-rich oxide scale on at least a portion of a surface thereof. Other embodiments relate to interconnects comprising a ferritic stainless steel and having a fuel side comprising metallic material that resists oxidation during operation of the SOFCs, and optionally include a nickel-base superalloy on the oxidant side thereof. Still other embodiments relate to ferritic stainless steels adapted for use as interconnects comprising ?0.1 weight percent aluminum and/or silicon, and >1 up to 2 weight percent manganese. Methods of making interconnects are also disclosed.

Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

Abstract: An article of manufacture selected from a titanium alloy fastener and a titanium alloy fastener stock including an alpha/beta titanium alloy comprising, in percent by weight: 3.9 to 5.4 aluminum; 2.2 to 3.0 vanadium; 1.2 to 1.8 iron; 0.24 to 0.3 oxygen; up to 0.08 carbon; up to 0.05 nitrogen; titanium; and up to a total of 0.3 of other elements. In certain embodiments, article of manufacture has an ultimate tensile strength of at least 170 ksi (1,172 MPa) and a double shear strength of at least 103 ksi (710.2 MPa). A method of manufacturing a titanium alloy fastener and a titanium alloy fastener stock comprising the alpha/beta alloy is disclosed.

Abstract: An alpha/beta titanium alloy comprising, in percent by weight based on total alloy weight: 3.9 to 4.5 aluminum; 2.2 to 3.0 vanadium; 1.2 to 1.8 iron; 0.24 to 0.30 oxygen; up to 0.08 carbon; up to 0.05 nitrogen; up to 0.015 hydrogen ; titanium; and up to a total of 0.30 of other elements. A non-limiting embodiment of the alpha/beta titanium alloy comprises an aluminum equivalent value in the range of 6.4 to 7.2, exhibits a yield strength in the range of 120 ksi (827.4 MPa) to 155 ksi (1,069 MPa), exhibits an ultimate tensile strength in the range of 130 ksi (896.3 MPa) to 165 ksi (1,138 MPa), and exhibits a ductility in the range of 12 to 30 percent elongation.

Abstract: System and method for providing control data for dynamically adjusting lighting and adjusting video pixel data for a display to substantially maintain image display quality while reducing power consumption. In accordance with one or more embodiments, image statistics, e.g., histogram data representing luma values corresponding to pixels for a video frame, are analyzed to determine whether the pixels represent one or more of a plurality of images which includes an image containing primarily natural imagery, an image containing primarily graphics imagery, and an image containing a combination of at least respective portions of natural and graphics imagery. Based on such analysis, control data are provided to enable light source brightness reduction by one of a plurality of percentages and pixel brightness increases, e.g.

Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.

Abstract: A system and method for configuring an integrated circuit. Embodiments include a method for manufacturing an integrated circuit (IC), comprising associating configuration items of the integrated circuit with at least one fuse of at least one type of fuse, wherein a fuse comprises a bit field and a physical fuse, and configuring the integrated circuit by setting the at least one fuse to a value, comprising logically combining multiple fuse values to determine a particular configuration, wherein at least one of the fuse values is not alterable after manufacture of the IC.