Patents Assigned to ATI
  • Method and apparatus with dynamic graphics surface memory allocation
    Patent number: 8212832
    Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 3, 2012
    Assignee: ATI Technologies ULC
    Inventors: Steve Stefanidis, Jeffrey G. Cheng, Philip J. Rogers
  • PHYSICALLY SMALL TUNABLE NARROW BAND ANTENNA
    Publication number: 20120162533
    Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.
    Type: Application
    Filed: March 2, 2012
    Publication date: June 28, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventor: Svetlan Milosevic
  • Displaying Compressed Supertile Images
    Publication number: 20120162250
    Abstract: A method for the display of compressed supertile images is disclosed. In one embodiment, a method for displaying an image frame from a plurality of compressed supertile frames includes: reading the compressed supertile frames; expanding the compressed supertile frames; and combining the expanded supertile frames to generate the image frame. The expanding can include generating an expanded supertile frame corresponding to each of the compressed supertile frames by inserting blank pixels for tiles in the expanded supertile frame that are not in the corresponding compressed supertile frame. Corresponding system and computer program products are also disclosed.
    Type: Application
    Filed: July 19, 2011
    Publication date: June 28, 2012
    Applicant: ATI Technologies ULC
    Inventor: David GLEN
  • MULTIPLE DISPLAY FRAME RENDERING METHOD AND APPARATUS
    Publication number: 20120154411
    Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventor: Jeffrey G. Cheng
  • METHOD AND APPARATUS FOR DATA TRANSFER
    Publication number: 20120159093
    Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 21, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Stephen L. Morein, Robert W. Bloemer
  • Wave guiding structures for crosstalk reduction
    Patent number: 8203395
    Abstract: Various apparatus and methods of addressing crosstalk in a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first layer of a circuit board with a first signal trace and forming a second layer of the circuit board with a second signal trace. A first guard trace is formed on the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace and a second guard trace is formed on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: June 19, 2012
    Assignee: ATI Technologies ULC
    Inventors: Fei Guo, Xiao Ling Shi, Mark Frankovitch, Wasim Ullah
  • Adaptive compression of video reference frames
    Patent number: 8204106
    Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: June 19, 2012
    Assignees: ATI Technologies, ULC, Advanced Micro Devices, Inc.
    Inventors: Greg Sadowski, Thomas E. Ryan, Daniel Wong, Paul Chow
  • Self-Refresh Panel Time Synchronization
    Publication number: 20120146968
    Abstract: In an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 14, 2012
    Applicant: ATI Technologies ULC
    Inventor: David Glen
  • METHOD AND APPARATUS FOR PROVIDING INDICATION OF A STATIC FRAME
    Publication number: 20120147020
    Abstract: A method and apparatus provides for providing an indication of a static frame. In one example, the method and apparatus notifies the arrival of a static frame by changing a vertical blanking interval for the static frame. For example, the method and apparatus may determine that a display frame is a static frame if no graphic processing activity and/or lack of update to the frame buffer have been detected for a period of time. In response to a display frame being a static frame, the method and apparatus may change the vertical blanking interval that is immediately before the static frame by increasing the number of blanking scan lines in the vertical blanking interval. The changed vertical blanking interval may be transmitted with the static frame as an indicator of the arrival of a static frame, so that the apparatus may enter a self-refresh mode to repeatedly display the static frame.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Syed A. Hussain, David I.J. Glen, Collis Quinn Carter, Andjelija Masnikosa
  • Advanced anti-aliasing with multiple graphics processing units
    Patent number: 8199164
    Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: June 12, 2012
    Assignee: ATI Technologies ULC
    Inventors: Raja Koduri, Gordon M. Elder, Jeffrey A. Golds
  • APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE
    Publication number: 20120144167
    Abstract: A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 7, 2012
    Applicant: ATI Technologies ULC
    Inventors: John S. Yates, JR., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
  • Apparatus and method for clean, rapidly solidified alloys
    Patent number: 8192681
    Abstract: One non-limiting embodiment of an apparatus for forming an alloy powder or preform includes a melting assembly, an atomizing assembly, and a collector. The melting assembly produces at least one of a stream of a molten alloy and a series of droplets of a molten alloy, and may be substantially free from ceramic in regions contacted by the molten alloy. The atomizing assembly generates electrons and impinges the electrons on molten alloy from the melting assembly, thereby producing molten alloy particles.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: June 5, 2012
    Assignee: ATI Properties, Inc.
    Inventors: Robin M. Forbes Jones, Richard L. Kennedy
  • Processing digital television programs at a receiver so as to prevent interception of unscrambled programs
    Patent number: 8196161
    Abstract: When a stream of packets (e.g. MPEG-2 transport stream) includes certain packets representing unscrambled digital television program content and certain other packets representing the content of a scrambled digital television program that is currently tuned by a receiver, interception of the unscrambled digital television program at an output of the receiver may be prevented by determining whether packets representing program content have an ascertained characteristic (e.g. have a packet ID matching one of a set of packet IDs) that uniquely identifies the packets as representing content of the scrambled program. For packets not having the characteristic, delivery to the output of the digital television receiver in an unscrambled state may be prevented, e.g., by discarding the packet or by overwriting its payload.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 5, 2012
    Assignee: ATI Technologies ULC
    Inventor: David A. Strasser
  • Semiconductor chip with reinforcing through-silicon-vias
    Patent number: 8193039
    Abstract: A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 5, 2012
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Integrated circuit having memory and router disposed thereon and method of making thereof
    Patent number: 8193635
    Abstract: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across at least one of the electrical leads associated with the carrier substrate. Thereupon, system instructions may be stored and retrieved from the system memory through the information router within the integrated circuit on the standard dimension carrier substrate.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: June 5, 2012
    Assignee: ATI Technologies ULC
    Inventor: John Bruno
  • METHOD AND APPARATUS FOR PROVIDING STATIC FRAME
    Publication number: 20120133659
    Abstract: A method and apparatus provides for providing a static frame. In one example, the method and apparatus divides a frame into regions and sends the divided regions of the frame from a display data transmitter, e.g., a processor such as a graphic processing unit (GPU), to a display data receiver, e.g., a timing controller (TCON). In a self-refresh mode when the frame is static, the method and apparatus detects alteration of one or more regions in the static frame. The alteration may be due to data errors in one or more regions of the static frame captured by the display data receiver and/or due to updated content (e.g., movement of a cursor) in one or more regions of the static frame in the display data transmitter. The method and apparatus then, in one example, only resends those altered regions from the display data transmitter to the display data receiver to redress the alteration.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Andjelija Masnikosa, Collis Quinn Carter
  • Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed
    Patent number: 8190944
    Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 29, 2012
    Assignee: ATI Technologies ULC
    Inventors: Kevin D. Senohrabek, Natale Barbiero, Gordon F. Caruk
  • Integrated circuit adapted to be selectively AC or DC coupled
    Patent number: 8188615
    Abstract: An integrated circuit is adapted to be selectively AC or DC coupled to an external device at a coupling point. The integrated circuit includes a first connector connected to the coupling point by way of a coupling capacitor for AC coupling, a second connector connected to the coupling point for DC coupling, and a switch to selectively short the first and second connectors and thereby the coupling capacitor, when the integrated circuit is DC coupled to the device. The switch may be a MOSFET bridge comprising a switch control MOSFET interconnected between the first and second connectors, with the switch control MOSFET receiving at its gate a mode status signal for turning on the switch control MOSFET and thereby shorting the MOSFET bridge when the integrated circuit is DC coupled to the external device.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 29, 2012
    Assignee: ATI Technologies ULC
    Inventors: Yamin Du, Richard Fung, Pouya Ashtiani
  • Apparatus and method for clean, rapidly solidified alloys
    Patent number: 8187358
    Abstract: One non-limiting embodiment of an apparatus for forming an alloy powder or preform includes a melting assembly, an atomizing assembly, and a field generating assembly, and a collector. The melting assembly produces at least one of a stream of a molten alloy and a series of droplets of a molten alloy, and may be substantially free from ceramic in regions contacted by the molten alloy. The atomizing assembly generates electrons and impinges the electrons on molten alloy from the melting assembly, thereby producing molten alloy particles. The field generating assembly produces at least one of an electrostatic field and an electromagnetic field between the atomizing assembly and the collector. The molten alloy particles interact with the at least one field, which influences at least one of the acceleration, speed, and direction of the molten alloy particles. Related methods also are disclosed.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: May 29, 2012
    Assignee: ATI Properties, Inc.
    Inventors: Robin M. Forbes Jones, Richard L. Kennedy
  • Method and apparatus for system time clock recovery
    Patent number: 8189730
    Abstract: Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: May 29, 2012
    Assignee: ATI Technologies ULC
    Inventor: Wai-Leong Poon