Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: An upscaler is disclosed that upscales each of a maximum value map, a minimum value map and an average value map to a destination resolution. A blending module generates a detail-enhanced upscaled image of the source image having the destination resolution by blending corresponding pixel values from an upscaled image of the source image with at least one of: the upscaled maximum value map and the upscaled minimum value map. The blending may be based on the strength of detected edges in the source image and further based on a comparison of each pixel value in the upscaled image with a corresponding pixel value in an average value map. A source image characteristic calculator may generate the maximum value map, the minimum value map and the average value map based on the intensity values of a source image.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A soil stabilizer for treating ground surface includes a stabilizer frame, a rotor rotatably mounted thereon, the rotor being movable such that the rotor may engage various depths of earth, a rotatable axle, and a track apparatus mounted on the rotatable axle, the track apparatus supporting the stabilizer frame and providing for movement of the stabilizer frame and rotor across the ground surface. The track apparatus may include a continuous flexible track having an upper length and a ground-engaging lower length and including an inner surface, an axle wheel mountable to the rotatable axle for rotational movement therewith, the axle wheel engaging the inner surface of the flexible track along the upper length to drive the flexible track in response to rotation of the axle, and a track apparatus frame for mounting the axle wheel.

Abstract: An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.

Abstract: A composite substrate includes first and second substrate layers with a polyurethane foam layer there between. The foam layer preferably penetrates into the first and second substrate layers to form very strong bonds without the need for intervening adhesives. A component of the foam material formulation is natural oil. The resultant composite substrate thereby has excellent load-bearing properties. It can also be manufactured with lower cost capital equipment and a reduced impact on the environment relative to substrates using more conventional foam formulations and bonding processes.

Abstract: An apparatus for rendering an image includes a command binning module. The command binning module generates binned image information by classifying command information into bins that each correspond to a display tile of an image to be rendered. The command binning module generates image depth information for each display tile based on the binned command information.

Abstract: A system and method using messages to access registers and memory in a PCI Express communications link environment. Vendor defined PCI Express messages can be used to read and write to the memory-mapped or register space of a device. Four types of accesses are defined using this messaging approach, namely memory read, memory write, configuration read and configuration write. The type of register access desired is defined by the appropriate value in a vendor-specific type field in the header of the vendor defined message. If a PCI Express compliant device at the other end of the PCI Express link does not support these types of messages, the messages are silently discarded by the receiver and no error is reported.

Abstract: A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element. The third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage. An error corrected difference is calculated between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.

Abstract: Certain embodiments of a melting and casting apparatus comprising includes a melting hearth; a refining hearth fluidly communicating with the melting hearth; a receiving receptacle fluidly communicating with the refining hearth, the receiving receptacle including a first outflow region defining a first molten material pathway, and a second outflow region defining a second molten material pathway; and at least one melting power source oriented to direct energy toward the receiving receptacle and regulate a direction of flow of molten material along the first molten material pathway and the second molten material pathway. Methods for casting a metallic material also are disclosed.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: A method comprises disabling a video digital-to-analog converter (DAC) that is configured to provide an output current representative of a video signal to an output node of an accessory connector in an enabled state. The accessory connector is coupleable to an accessory device. The method further comprises determining, while the video DAC is disabled, whether the accessory connector is coupled to the accessory device based on a voltage at the output node while the output node is connected to the first voltage reference via a resistor having a resistance.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

Abstract: A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters.