Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In an embodiment, the vapor configuration is modified to include fins that define a cross-flow heat exchanger where the vapor from the vapor chamber serves as the fluid in the vertical cross-flow in the heat exchanger and natural or forced cooling air serves as the horizontal cross-flow for the heat exchanger.

Abstract: A linearly actuated switch assembly is adjustably disposed in a housing stem bore of a robotic crash protector device. An actuation plate is disposed over the central bore of the contact surface. As the piston moves toward the housing base in response to a crash force or torque applied to the actuator, the actuation plate moves in an axial direction, and contacts and actuates the switch. The actuation plate is biased towards the contact surface by an actuation spring disposed between the actuation plate and a spring plate that is rigidly affixed to the housing stem. This arrangement allows the actuation plate to “float” with respect to the fixed spring plate. In particular, the actuation plate may assume the orientation of the piston, which may be canted from its default orientation—normal to the device central axis—by uneven application of force by the actuator.

Abstract: A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like.

Abstract: A nucleated casting apparatus including an atomizing nozzle configured to produce a droplet spray of a metallic material, a mold configured to receive the droplet spray and form a preform therein, and a gas injector which can limit, and possibly prevent, overspray from accumulating on the mold. The gas injector can be configured to produce a gas flow which can impinge on the droplet spray to redirect at least a portion of the droplet spray away from a side wall of the mold. In various embodiments, the droplet spray may be directed by the atomizing nozzle in a generally downward direction and the gas flow may be directed in a generally upward direction such that the gas flow circumscribes the perimeter of the mold.

Abstract: A method and apparatus that partitions a single display's viewable area into at least two virtual viewable areas, and emulates the at least two virtual viewable areas as at least two emulated physical displays with an operating system such that the operating system behaves as if interfacing with at least two actual independent physical displays. The method provides the operating system with generated display identification data (such as “EDID”) for each of the emulated physical displays in response to a query from the operating system. The method and apparatus also receive notification of an interrupt (where the interrupt corresponds to the single physical display), and reports to the operating system with at least two sets of interrupt reporting information, corresponding to the at least two emulated physical displays, as if two interrupts were received. The operating system is thereby “faked” into acting as if two physical displays are in operation.

Abstract: Various non-limiting embodiments disclosed herein relate to nozzle assemblies for conveying molten material, the nozzle assemblies comprising a body, which may be formed from a material having a melting temperature greater than the melting temperature of the molten material to be conveyed, and having a molten material passageway extending therethrough. The molten material passageway comprises an interior surface and a protective layer is adjacent at least a portion of the interior surface of the passageway. The protective layer may comprise a material that is essentially non-reactive with the molten material to be conveyed. Further, the nozzle assemblies according to various non-limiting embodiments disclosed herein may be heated, and may be self-inspecting. Methods and apparatus for conveying molten materials and/or atomizing molten materials using the nozzle assemblies disclosed herein are also provided.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A digital interface device is provided for facilitating key encryption of a digital signal which is communicated from a computer system to an associated peripheral device, such as a digital display device. The digital interface device has a digital output, digital output formatting circuitry associated with the output and a non-volatile RAM for storing a basic input/output system (BIOS) for, inter alia, controlling digital output formatting. The interface device is configured such that the non-volatile RAM has a specific addressable write-protectable area allocated for storing an encryption key flag at a flag address along with encryption key data. The write-protectable area is rendered read-only when a predetermined flag value is stored at the flag address.

Abstract: A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: Methods for producing zirconium strips that demonstrate improved formability are disclosed. The zirconium strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed substantially pure zirconium strip, articles of manufacture produced from the substantially pure zirconium strip, and methods for making the articles of manufacture.

Abstract: An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.

Abstract: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.

Abstract: A circuit includes an enhanced frequency range linear pulse code modulation conversion circuit. The enhanced frequency range linear pulse code modulation conversion circuit is driven by a clock signal within a frequency range. The enhanced frequency range linear pulse code modulation conversion circuit provides enhanced frequency range linear pulse code modulated information. More specifically, the enhanced frequency range linear pulse code modulation conversion circuit is provided by selectively decimating and interpolating non-enhanced frequency range linear pulse code modulated information based on a desired output sampling frequency and the frequency range.

Abstract: The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.