Abstract: Methods for making brines may generally comprise forming a mixture comprising: (i) a solid material produced as a by-product of the Kroll process including solid anhydrous magnesium chloride and solid elemental magnesium; (ii) an amount of a previously-produced brine; and (iii) an amount of water sufficient to provide a predetermined brine concentration. At least a portion of the solid material in the mixture is dissolved while simultaneously controlling the temperature of the mixture. At least a portion of insoluble matter is separated from the mixture.
Abstract: A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system.
Abstract: A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system.
Abstract: Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.
Type:
Application
Filed:
April 16, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Michael J. MANTOR, Jeffrey T. Brady, Christopher L. Spencer, Daniel W. Wong, Andrew E. Gruber
Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.
Type:
Application
Filed:
January 28, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Abstract: A method of power management is provided. The method includes detecting an event, assign a first responsibility to a first graphics processing unit (GPU) and a second responsibility to second GPU, and changing a power state of the first and second GPUs based on the first and second responsibilities, respectively. The first responsibility is different from the second responsibility.
Abstract: A method of operating a device is provided. The method includes transitioning the GPU to a substantially disabled state in response to a first received signal, and generating, while the GPU is in the substantially disabled state, a response signal in response to a second received signal. The response signal is substantially similar to a second response signal that would be generated by the GPU in a powered state in response to the second received signal.
Type:
Application
Filed:
February 26, 2010
Publication date:
March 10, 2011
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Oleksandr KHODORKOVSKY, Ali Ibrahim, Phil Mummah
Abstract: Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.
Type:
Application
Filed:
March 8, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
David I.J. GLEN, Philip J. Rogers, Gordon F. Caruk, Gongxian Jeffrey Cheng, Mark Hummel, Stephen Patrick Thompson, Anthony Asaro
Abstract: The present invention provides an analysis method that uses error metrics to determine whether an image is suitable for compression. One embodiment of the present invention can make the determination in real-time. In one embodiment, analysis methods based on four error metrics are used to determine whether a compressed image should be used. The first metric is a signal-to-noise (SNR) error metric that prevents compressed images with low SNR from being used to represent original images. Another metric is detecting the geometric correlation of pixels within individual blocks of the compressed images. The third metric is used to determine whether color mapping in the compressed images are well-mapped. A final metric is a size metric that filters images smaller than a certain size and prevents them from being compressed. As most analysis methods are integral parts of the compression process, the present invention incurs little cost collecting error metric data.
Type:
Grant
Filed:
October 29, 2002
Date of Patent:
March 8, 2011
Assignee:
ATI Technologies ULC
Inventors:
David Oldcorn, Andrew Pomianowski, Raja Koduri
Abstract: An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.
Type:
Grant
Filed:
August 15, 2007
Date of Patent:
March 8, 2011
Assignee:
ATI Technologies ULC
Inventors:
Aris Balatsos, Charles Leung, Siva Raghu Ram Voleti
Abstract: A precipitation hardenable martensitic stainless steel that includes, in percent by weight, 11.0 to 12.5 percent chromium, 1.0 to 2.5 percent molybdenum, 0.15 to 0.5 percent titanium, 0.7 to 1.5 percent aluminum, 0.5 to 2.5 percent copper, 9.0 to 11.0 percent nickel, up to 0.02 percent carbon, up to 2.0 percent tungsten, and up to 0.001 percent boron. Articles formed from the stainless steel and methods of forming the same are also disclosed.
Abstract: A method detects by a display driver logic, inactivity between the display driver logic and a display logic, and deactivates an auxiliary channel by the display driver logic, wherein the auxiliary channel is between the display driver logic and the display logic. The method also detects, by the display driver logic via the auxiliary channel, a required operating mode capability of a display; and determines a minimum number of connection lines needed between the display driver logic and the display logic, to operate the display in the required operating mode capability. A display driver logic includes a connection port suitable for operative connection to a display logic, wherein the display drive logic is operative to detect inactivity between the display driver logic and the display logic, and deactivate an auxiliary channel between the display driver logic and the display logic.
Abstract: An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.
Type:
Application
Filed:
August 24, 2010
Publication date:
March 3, 2011
Applicant:
ATI TECHNOLOGIES ULC
Inventors:
David I.J. Glen, Collis Quinn Carter, Natan Shtutman, Gabriel Abarca, Jonathan Wang
Abstract: A tool for removing material from a surface includes a body defining a longitudinal bore and an opening connecting an outer surface of the body to the longitudinal bore. A cutting element comprising a cutting surface is dimensioned to be at least partially received by the opening. The cutting surface is configured to translate from a first position to a second position in response to a centrifugal force. In the second position the cutting surface is extended outwardly through the opening, beyond the outer surface of the body. In one example, the tool may be used to remove material, such as oxidation, from the inner walls of a cylindrical article selected from a pipe and a tube.
Abstract: An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.
Type:
Application
Filed:
August 24, 2010
Publication date:
March 3, 2011
Applicant:
ATI TECHNOLOGIES ULC
Inventors:
David I.J. Glen, Collis Quinn Carter, Natan Shtutman, Ngar Sze Nancy Chan, Michael Foxcroft
Abstract: A method is disclosed that provides, by mapping logic, output to a selected display of a plurality of displays forming an arrangement, where the selected display provides a visual indication in response to the output. The visual indication indicates that the selected display is ready to be mapped to an image data portion corresponding to the selected display's physical position within the arrangement. The method maps the image data portion to the selected display. The image data portion is stored in a frame buffer, and is mapped in response to input indicating the selected display's physical position. The frame buffer stores a single large surface image as a plurality of image data portions, where each image data portion is mapped to a corresponding display of the plurality of displays. An apparatus is also disclosed, that operates in accordance with the method.
Type:
Application
Filed:
August 24, 2009
Publication date:
February 24, 2011
Applicant:
ATI Technologies ULC
Inventors:
Stephen J. Orr, Christina M. Elder, Wenzhan Xie, Jianping Ji
Abstract: An electrical connector, such as a circuit board connector, includes a first group or subassembly of electrical contacts physically separate from an adjacent and second group or subassembly of contacts. The first group of electrical contacts and second group of electrical contacts each include a row of lower contacts and upper contacts. The second group of electrical contacts has an identical but mirrored configuration as the first group of electrical contacts.
Abstract: A circuit includes a plurality of display path circuits and a timing and frame synchronization circuit. The timing and frame synchronization circuit aligns a first blanking interval of first timing information provided by a first of the display path circuits for a first display based on a second blanking interval of second timing information provided by a second of the display path circuits for a second display.
Abstract: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented current sources selectively generate source currents to adjust the output voltage levels as the differential output terminals in response to the current source control signal. The digital data transmitting device may also include a current bulk biasing circuit that generates a current source bulk biasing signal such that when the differential signaling circuitry is in one mode of operation, the current source bulk biasing signal retards currents leakage across the pair of transistor-implemented current sources.
Abstract: In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.