Patents Assigned to Avalanche Technology, Inc.
  • MRAM etching processes
    Patent number: 8975088
    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Parviz Keshtbod, Roger K. Malmhall
  • Method for forming MTJ memory element
    Patent number: 8975089
    Abstract: The present invention is directed to a method for forming a magnetic tunnel junction (MTJ) memory element comprising the steps of providing a substrate having a bottom electrode layer thereon; depositing an MTJ layer stack on top of the bottom electrode layer; forming a composite hard mask comprising a bottom conducting mask disposed on top of the MTJ layer stack and a top conducting mask with a dielectric mask interposed therebetween; etching the MTJ layer stack with the composite hard mask thereon to form a patterned MTJ while consuming the top conducting mask, thereby exposing the dielectric mask on top; and trimming the patterned MTJ with the bottom conducting mask and the dielectric mask thereon by ion beam etching to remove redeposited material and damaged material from surface of the patterned MTJ while consuming most of the dielectric mask.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Dong Ha Jung, Kimihiro Satoh, Jing Zhang, Yiming Huai
  • Initialization method of a perpendicular magnetic random access memory (MRAM) device
    Patent number: 8971100
    Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai
  • Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)
    Patent number: 8971107
    Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Petro Estakhri, Ebrahim Abedifard, Frederick Jaffin, Siamack Nemazie
  • Method of manufacturing magnetic tunnel junction memory element
    Patent number: 8962349
    Abstract: The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Benjamin Chen, Kimihiro Satoh, Jing Zhang, Dong Ha Jung
  • Storage processor managing NVME logically addressed solid state disk array
    Patent number: 8966164
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 24, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Secure spin torque transfer magnetic random access memory (STTMRAM)
    Patent number: 8954759
    Abstract: A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Ngon Van Le
  • Method of LUN management in a solid state disk array
    Patent number: 8954658
    Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Ruchirkumar D. Shah
  • Storage processor managing solid state disk array
    Patent number: 8954657
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing stripping across the SSDs.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Host-managed logical mass storage device using magnetic random access memory (MRAM)
    Patent number: 8947937
    Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventor: Mehdi Asnaashari
  • High capacity low cost multi-stacked cross-line magnetic memory
    Patent number: 8947919
    Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Method and apparatus for reading a magnetic tunnel junction using a sequence of short pulses
    Patent number: 8947922
    Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20150032943
    Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.
    Type: Application
    Filed: February 27, 2014
    Publication date: January 29, 2015
    Applicant: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Method for magnetic screening of arrays of magnetic memories
    Patent number: 8942032
    Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiments the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: January 27, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Ebrahim Abedifard, Yiming Huai
  • HOST-MANAGED Logical MASS STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20150026392
    Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.
    Type: Application
    Filed: February 28, 2014
    Publication date: January 22, 2015
    Applicant: Avalanche Technology, Inc.
    Inventor: Mehdi Asnaashari
  • Method for reducing effective raw bit error rate in multi-level cell NAND flash memory
    Patent number: 8935599
    Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: January 13, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Anilkumar Mandapuram
  • Controller management of memory array of storage device using magnetic random access memory (MRAM)
    Patent number: 8929146
    Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 6, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Multi-state spin-torque transfer magnetic random access memory
    Patent number: 8917543
    Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: December 23, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ)
    Patent number: 8917546
    Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Storage system employing MRAM and physically addressed solid state disk
    Patent number: 8909855
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 9, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie