Patents Assigned to Avalanche Technology, Inc.
  • Spin transfer torque magnetic random access memory (STTMRAM) having graded synthetic free layer
    Patent number: 8779537
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 15, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger Klas Malmhall, Yuchen Zhou
  • MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20140192590
    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY
    Publication number: 20140192591
    Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 10, 2014
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventor: Parviz Keshtbod
  • MTJ MRAM with stud patterning
    Patent number: 8772888
    Abstract: Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Dong Ha Jung, Kimihiro Satoh, Jing Zhang, Yuchen Zhou, Yiming Huai
  • Spin transfer torque magnetic random access memory (STTMRAM) having graded synthetic free layer
    Patent number: 8772886
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 8, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Ioan Tudosa, Roger Klas Malmhall, Yuchen Zhou
  • MEMORY SENSING CIRCUIT
    Publication number: 20140185372
    Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 3, 2014
    Applicant: Avalanche Technology, Inc.
    Inventor: Parviz Keshtbod
  • MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER AND INTERFACIAL ANISOTROPIC FREE LAYER
    Publication number: 20140183608
    Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.
    Type: Application
    Filed: March 5, 2014
    Publication date: July 3, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Huadong Gan, Yiming Huai, Xiaobin Wang, Yuchen Zhou, Zihui Wang
  • STT-MRAM MTJ manufacturing method with in-situ annealing
    Patent number: 8758850
    Abstract: A spin transfer torque magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai
  • Magnetic memory write circuitry
    Patent number: 8760914
    Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 24, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Parviz Keshtbod
  • METHOD AND APPARATUS FOR SENSING THE STATE OF A MAGNETIC TUNNEL JUNCTION (MTJ)
    Publication number: 20140169079
    Abstract: A method of measuring the resistance of a magnetic tunnel junction (MTJ) is performed by selecting the MTJ to be measured, the MTJ having a resistance associated therewith and coupled to an access transistor. Further, measuring a voltage at an end of the MTJ that is coupled to the access transistor and measuring voltage, V0, at the coupling of the selected MTJ and the associated access transistor, turning off a decoder that is coupled to the MTJ, and after applying current, measuring the applied current and using the measured applied current to determine the resistance of the MTJ.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK
    Publication number: 20140170776
    Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Dong Ha Jung, Jing Zhang, Benjamin Chen, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou
  • MAGNETORESISTIVE LAYER STRUCTURE WITH VOLTAGE-INDUCED SWITCHING AND LOGIC CELL APPLICATION
    Publication number: 20140169083
    Abstract: Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By taking advantage of the electrical field induced anisotropy combining with the spin torque effect, free layer-1 and free layer-2 can be controlled individually by voltage pulses having selected sign (polarity) and amplitude characteristics. The MTJ cell structure can be used as a fully functional logic cell with two input bit values corresponding to the high or low resistance of the two sub-MTJ structures and the output of a logical operation, e.g. an XOR function, determined by the resistance state of each MTJ cell.
    Type: Application
    Filed: August 27, 2013
    Publication date: June 19, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Zihui Wang, Yuchen Zhou, Yiming Huai
  • Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)
    Patent number: 8755221
    Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 17, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Petro Estakhri, Ebrahim Abedifard, Frederick Jaffin, Siamack Nemazie
  • Memory with on-chip error correction
    Patent number: 8751905
    Abstract: A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER
    Publication number: 20140151827
    Abstract: The present invention is directed to an STT-MRAM device including a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Yuchen Zhou, Zihui Wang, Huadong Gan, Yiming Huai
  • MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20140143481
    Abstract: An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.
    Type: Application
    Filed: December 17, 2013
    Publication date: May 22, 2014
    Applicant: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • HIGH DENSITY RESISTIVE MEMORY HAVING A VERTICAL DUAL CHANNEL TRANSISTOR
    Publication number: 20140138609
    Abstract: Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.
    Type: Application
    Filed: March 15, 2013
    Publication date: May 22, 2014
    Applicant: AVALANCHE TECHNOLOGY INC.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Dong Ha Jung
  • CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20140143489
    Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.
    Type: Application
    Filed: July 26, 2013
    Publication date: May 22, 2014
    Applicant: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20140143480
    Abstract: An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 22, 2014
    Applicant: Avalanche Technology, Inc.
    Inventor: Mehdi Asnaashari
  • Embedded magnetic random access memory (MRAM)
    Patent number: 8730716
    Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 20, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard