Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.

Abstract: The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines.

Abstract: A method of writing to a magneto tunnel junction (MTJ) includes writing data to the MTJ, reading the written data using a first reference MTJ and reading the written data using a second reference MTJ. Based on the reading steps and the result of the comparing step, setting a select bit to select the proper reference for future reads.

Abstract: Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By taking advantage of the electrical field induced anisotropy combining with the spin torque effect, free layer-1 and free layer-2 can be controlled individually by voltage pulses having selected sign (polarity) and amplitude characteristics. The MTJ cell structure can be used as a fully functional logic cell with two input bit values corresponding to the high or low resistance of the two sub-MTJ structures and the output of a logical operation, e.g. an XOR function, determined by the resistance state of each MTJ cell.

Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.

Abstract: A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Abstract: A spin-transfer torque memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract: A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer.

Abstract: A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components.

Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.

Abstract: A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.

Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.

Abstract: A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided.

Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.