Patents Assigned to Avalanche Technology
  • Publication number: 20120295370
    Abstract: A STTMRAM element has a free sub-layer with enhanced internal stiffness. A first free sub-layer is made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, with an amount greater than the amount of B in the first free sub-layer. The STTMRAM element is cooled to a second temperature that is lower than the first temperature and a third free sub-layer is deposited directly on top of the second free layer, with the third free sub-layer being made partially of boron B. The amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: November 22, 2012
    Applicant: AVALANCHE TECHNOLOGY INC.
    Inventors: Yuchen Zhou, Yiming Huai
  • Patent number: 8313960
    Abstract: A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 20, 2012
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 8310020
    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 13, 2012
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20120280339
    Abstract: A STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.
    Type: Application
    Filed: June 15, 2011
    Publication date: November 8, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Jing Zhang, Yuchen Zhou, Rajiv Yadav Ranjan, Yiming Huai
  • Publication number: 20120282711
    Abstract: A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.
    Type: Application
    Filed: February 10, 2012
    Publication date: November 8, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Publication number: 20120275219
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 1, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventor: Ebrahim Abedifard
  • Patent number: 8295083
    Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: October 23, 2012
    Assignee: Avalanche Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Publication number: 20120264234
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 18, 2012
    Applicant: AVALANCHE TECHNOLOGY INC.
    Inventors: Yuchen Zhou, Yiming Huai
  • Patent number: 8289757
    Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: October 16, 2012
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Publication number: 20120241826
    Abstract: A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Kimihiro Satoh, Ebrahim Abedifard
  • Publication number: 20120230095
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Publication number: 20120230101
    Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 13, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Ebrahim ABEDIFARD, Petro ESTAKHRI
  • Publication number: 20120217595
    Abstract: A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.
    Type: Application
    Filed: November 4, 2011
    Publication date: August 30, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Yuchen Zhou, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Roger Klas Malmhall
  • Publication number: 20120212998
    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 23, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20120205760
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 16, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan
  • Publication number: 20120205761
    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20120205763
    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20120206958
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 16, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan, Jing Zhang
  • Patent number: 8238145
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: August 7, 2012
    Assignee: Avalanche Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Publication number: 20120188818
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 26, 2012
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall