Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer.

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.

Abstract: A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiments the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer and made of an iron platinum alloy with at least one of X or Y material, X being from a group consisting of: boron (B), phosphorous (P), carbon (C), and nitride (N) and Y being from a group consisting of: tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), silicon (Si), copper (Cu), silver (Ag), aluminum (Al), chromium (Cr), tin (Sn), lead (Pb), antimony (Sb), hafnium (Hf) and bismuth (Bi), molybdenum (Mo) or rhodium (Ru), the magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate.

Abstract: A method and apparatus for accessing a storage media employed to store data from a host includes identifying a module as a block storage device. The block storage device is coupled to a host and includes a bridge controller and magnetic random access memory (MRAM). The MRAM has a buffer window for storing data from a host, the buffer window is movable throughout the MRAM. The bridge controller has a bridge controller buffer and controller registers. A request to access the block storage device is intercepted and a command to the block storage device is issued. If the command is a write command, at least a portion of the data to be saved into the MRAM is saved. The size of the at least a portion of the data is based on the capacity of the bridge controller buffer. Further, at least a portion of the data to the buffer window is transferred and upon having additional data to be saved into the MRAM, the buffer window is moved within the MRAM.

Abstract: The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same.

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

Abstract: A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.

Abstract: A method of writing to a magnetic memory cell that includes selecting a magnetic memory cell having a pair of MTJs, and based on whether the selected magnetic memory cell is an ‘odd’ magnetic memory cell or an ‘even’ magnetic memory cell and a state to which the selected magnetic memory cell is being written, setting a distinct bit line (BL), coupled to a first MTJ of the pair of MTJs or a second MTJ of the pair of MTJs, to a voltage level indicative of a certain state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the first or second MTJs to be in a direction opposite to that of the other one of the first or second MTJs to program the first and second MTJs in opposite states.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: A method of writing to a magnetic memory cell that includes selecting a magnetic memory cell having a pair of MTJs, and based on whether the selected magnetic memory cell is an ‘odd’ magnetic memory cell or an ‘even’ magnetic memory cell and a state to which the selected magnetic memory cell is being written, setting a distinct bit line (BL), coupled to a first MTJ of the pair of MTJs or a second MTJ of the pair of MTJs, to a voltage level indicative of a certain state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the first or second MTJs to be in a direction opposite to that of the other one of the first or second MTJs to program the first and second MTJs in opposite states.

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.