Abstract: A method of making an optoelectronic semiconductor package device includes attaching a conductive trace to a semiconductor chip using a transparent adhesive, wherein the chip includes an upper surface and a lower surface, and the upper surface includes a light sensitive cell and a conductive pad, then forming an encapsulant that covers the lower surface, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a metal base, wherein the chip includes a conductive pad, and the conductive trace is disposed between the metal base and the chip, then forming a through-hole that extends through the metal base and exposes the conductive trace and the pad, then forming a connection joint that contacts and electrically connects the conductive trace and the pad in the through-hole, and then etching the metal base, thereby reducing contact area between the metal base and another material. Preferably, the through-hole extends through an insulative adhesive that attaches the conductive trace to the chip, and etching the metal base reduces contact area between the metal base and the connection joint.

Abstract: A method of making a semiconductor package device includes attaching a semiconductor chip to a metallic structure using an insulative adhesive, wherein the chip includes a conductive pad, the metallic structure includes first and second opposing surfaces and a lead, the adhesive is disposed between the first surface and the chip, the lead includes a recessed portion, a non-recessed portion and opposing outer edges between the first and second surfaces that extend across the recessed and non-recessed portions, and the recessed portion is recessed relative to the non-recessed portion at the second surface, forming an encapsulant that contacts the chip, the first surface, the outer edges and the recessed portion, wherein the encapsulant completely covers the chip, the outer edges and the recessed portion without completely covering the non-recessed portion, and forming a connection joint that electrically connects the lead and the pad.

Abstract: A semiconductor package device includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another inside the insulative housing and outside the chip.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes first and second opposing major surfaces, wherein the first surface of the chip includes a conductive pad, a substrate that includes first and second opposing major surfaces, wherein the first and second surfaces of the substrate include a conductive terminal and a dielectric base, the conductive terminal extends through the dielectric base to the first and second surfaces of the substrate, a cavity extends from the first surface of the substrate into the substrate, the first surfaces of the chip and the substrate face in a first direction, the second surfaces of the chip and the substrate face in a second direction, and the chip extends into the cavity, a conductive trace in an electrically conductive path between the conductive terminal and the pad, and an adhesive disposed between the conductive trace and the chip, the conductive trace and the substrate, and the chip and the substrate.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a conductive trace and a substrate, wherein the chip includes first and second opposing major surfaces and a conductive pad, the pad extends to the first surface of the chip, the substrate includes first and second opposing major surfaces, a conductive terminal and a dielectric base, the conductive terminal extends through the dielectric base to the first and second surfaces of the substrate, a cavity extends from the first surface of the substrate into the substrate, the first surfaces of the chip and the substrate face in a first direction, the second surfaces of the chip and the substrate face in a second direction, and the chip extends into the cavity, and then electrically connecting the conductive terminal to the pad using the conductive trace.

Abstract: A test probe includes a conductive trace with a bumped terminal, the bumped terminal includes a jagged contact surface and a cavity that face in opposite directions, and the contact surface includes a plated metal. The contact surface is jagged due to particles which may protrude, be covered or dislodged. Preferably, the test probe includes an elastomer that fills the cavity so that the bumped terminal is compliant. The test probe is well-suited for pressure contact with semiconductor chips, BGA packages and other electronic devices.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract: An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a bumped terminal, the metal base and the routing line are disposed on opposite sides of the insulative base, and the bumped terminal includes a cavity that extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the bumped terminal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, the pillars are disposed outside the peripheries of the chips and aligned with one another, and the first pillar extends into a cavity in the second pillar. The conductive bond is within the cavity and contacts and electrically connects the pillars.

Abstract: A method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the terminal protrudes downwardly from and extends through a bottom surface of the housing, the lead protrudes laterally from and extends through a side surface of the housing, and the terminal and the lead are electrically connected to one another and a chip pad inside the housing, attaching the device to a test socket that electrically contacts the lead without electrically contacting the terminal, testing the test socket, and removing the device from the test socket. The method may include trimming the lead after removing the device from the test socket and the attaching the device to a printed circuit board that electrically contacts the terminal without electrically contacting the lead.

Abstract: A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The conductive trace includes a terminal that extends through the central portion and a lead that protrudes laterally from and extends through the side surface. The second device includes a second semiconductor chip, extends into the cavity and is positioned within and does not extend outside a periphery of the cavity. The conductive bond is inside the cavity, on the terminal and contacts and electrically connects the first and second devices.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, providing a conductive trace and a metal base, wherein the conductive trace includes a routing line and a contact terminal, the routing line is disposed outside the metal base, the contact terminal extends from the routing line through the metal base, the contact terminal includes a plated metal that contacts and extends through the metal base, the plated metal forms a peripheral sidewall portion of the contact terminal, and the plated metal surrounds a central surface area without extending into the central surface area, then mechanically attaching the chip to the conductive trace, removing a portion of the metal base that contacts the plated metal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The first conductive trace includes a first terminal that extends through the central portion. The second device includes a second insulative housing, a second semiconductor chip and a second conductive trace. The second insulative housing includes a second bottom surface. The second conductive trace includes a second terminal that extends through the second bottom surface. The conductive bond contacts and electrically connects the terminals, and the second terminal extends into the cavity.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip with upper and lower surfaces, wherein the upper surface includes a conductive pad, providing a conductive trace, then disposing an insulative adhesive between the conductive trace and the chip, thereby mechanically attaching the conductive trace to the chip such that the conductive trace overlaps the pad, the adhesive contacts and is sandwiched between the conductive trace and the pad, and the conductive trace and the pad are electrically isolated from one another, then removing the adhesive between the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the adhesive is removed by laser ablation then plasma etching.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract: A method of manufacturing a multilayer interconnect substrate includes providing a first interconnect layer that includes a first conductive trace, wherein the first conductive trace includes a first pillar and a first routing line, and the first pillar protrudes vertically from and is electrically connected to the first routing line, providing a second interconnect layer that includes a second conductive trace, wherein the second conductive trace includes a second pillar and a second routing line, and the second pillar protrudes vertically from and is electrically connected to the second routing line, forming an opening in a dielectric layer between the first and second interconnect layers that exposes portions of the first pillar and the second routing line that were previously covered by the dielectric layer, and forming a connection joint in the opening that contacts and electrically connects the first pillar and the second routing line.