Abstract: A system and method for adjusting a level of compression for thin and chubby computing clients. End devices in a network can stream audio/video traffic over a network. Such a connection between the end devices can be reserved with guarantees of bandwidth and latency being obtained. Bandwidth guarantees across multiple intermediary switches can be used to define a compression level for the end devices. In one embodiment, the lowest compression level that will produce audio/video traffic that will fit in the guaranteed connection bandwidth is chosen to produce the highest quality audio/video stream.

Abstract: A secure processor in a PC-slave device manages secure loading of execution code and/or data, which is stored, in encrypted form, in a PC hard-drive. The secure processor causes decryption of the execution code and/or data by the PC-slave device, and storage of the decrypted execution code and/or data in a restricted portion of a memory that is dedicated for use by the PC-slave device, with the restricted portion of the dedicated memory being only accessible by the PC-slave device. The secure processor validates decrypted execution code and/or data. The secure processor blocks operations of a main processor in the PC-slave device during secure loading of execution code and/or data, and discontinues that blocking after validating the decrypted execution code and/or data. The secure processor stores encryption keys that are utilized during decryption of the encrypted execution code and/or data.

Abstract: A method and system for communicating feedback information in a multiple user multiple input multiple output (MU-MIMO) communication system are presented. In one aspect of the method and system, a beamformer station may communicate a feedback information request to a plurality of beamformee stations. The feedback information request may request feedback data for a plurality of RF channel bands. The RF channel bands may form a multichannel. The beamformer may subsequently transmit a plurality of signals utilizing the RF channel bands within the multichannel. Each of the beamformees may receive the plurality of subsequently transmitted signals. A beamformee may generate the requested feedback data for each RF channel band within the multichannel. The beamformee may generate a beamforming report, which comprises the feedback data, which is generated across the plurality of RF channel bands in the multichannel. The beamformee may transmit the beamforming report to the beamformer.

Abstract: A wireless device includes processing circuitry, a receiver section, a transmitter section, and an antenna. The processing circuitry determines a set of information signals of a RF Multiple Frequency Bands Multiple Standards (MFBMS) signal. The receiver section down-converts a portion of the RF MFBMS signal by one or more respective shift frequencies to produce a corresponding baseband/low Intermediate Frequency (BB/IF) information signal from which the processing circuitry extracts data. The transmitter section converts a respective BB/IF information signal received from the processing circuitry by a respective shift frequency to produce a corresponding RF information signal and a combiner that combines the RF information signals to form a RF MFBMS signal. The receiver section and the transmitter section include ADCs and/or DACs, respectively, that are adjustable based upon characteristics of the RF MFBMS signal, the BB/IF MFBMS signal, and/or based upon signals carried therein, e.g.

Abstract: Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.

Abstract: Aspects of a method and system for medium access control (MAC) layer specialization for voice and multimedia data streams are presented. Aspects of the method include determining a number of attempts for transmitting one or more medium access control (MAC) frames. Aspects of the system may include a processor that enables determination of a number of attempts for transmitting one or more MAC frames. A maximum number for such attempts may be determined based on one or more priority levels associated with different portions of multimedia information being communicated via a wireless medium and contained within the one or more MAC frames.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A MIMO pre-coding system for a delta quantizer for MIMO pre-coders with finite rate channel state information feedback may include quantizing a change in channel state information in a MIMO pre-coding system onto a codebook, which comprises one or more unitary matrices, using a cost function. The codebook may be generated based on at least the channel state information. The channel state information may comprise a matrix V and the cost function f(A) may be defined by the following relationship: f ? ( A ) = ( 1 N ? ? j = 1 N ? ? a jj ? 2 ) where A is a matrix of size N by N and aij is element (i,j) of matrix A. One or more unitary matrices may be generated from at least a first set of matrices and a second set of matrices, where the first set of matrices may comprise one or more Givens matrices. A dynamic range and a resolution of the codebook may be modified.

Abstract: Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.

Abstract: A method and system for secure and scalable key management for cryptographic processing of data is described herein. In the method, a General Purpose Cryptographic Engine (GPE) receives key material via a secure channel from a key server and stores the received Key encryption keys (KEKs) and/or plain text keys in a secure key cache. When a request is received from a host to cryptographically process a block of data, the requesting entity is authenticated using an authentication tag included in the request. The GPE retrieves a plaintext key or generate a plaintext using a KEK if the authentication is successful, cryptographically processes the data using the plaintext key and transmits the processed data. The system includes a key server that securely provides encrypted keys and/or key handles to a host and key encryption keys and/or plaintext keys to the GPE.

Abstract: An integrated circuit radio transceiver and method therefor comprises a receiver front end that further includes a plurality of in-phase and quadrature phase receive processing block operable at first and second frequency bands wherein each of the receive processing blocks defines an ingoing signal path and further includes a plurality of filtering and amplification blocks disposed within the corresponding ingoing signal path, a plurality of RSSI blocks coupled to receive an ingoing analog signal from a corresponding plurality of nodes disposed throughout the ingoing signal path, each of the plurality of received signal strength indicator blocks producing a signal strength indication, and wherein a baseband processor is operable to receive a selected signal strength indication and to produce at least one gain setting to at least one amplification block within the in-phase or quadrature phase receive processing blocks.

Abstract: A communication system performs burst noise cancellation. A transmitter produces and transmits a spread signal that comprises at least one known-value symbol spread by a plurality of non data-carrying orthogonal codes and data symbols spread by at least one data-carrying orthogonal code. The transmitter transmits the spread signal across a communication link that introduces burst noise. A burst noise detector determines burst noise affected chips of the orthogonal codes. A weight computation functional block calculates a plurality of complex-valued combining weights based upon the burst noise affected chips. A vector de-spreader and a linear combiner operate in combination to use the plurality of non data-carrying orthogonal codes, the at least one data-carrying orthogonal code, and the plurality of complex-valued combining weights to de-spread the received spread signal to produce the data symbols with the burst noise substantially removed.

Abstract: A secure digital system including a number of ICs that exchange data among each other. Each of the ICs includes a key generator for generating a cipher key; a memory for securely storing the generated cipher key; an authenticating module for authenticating neighboring ICs of a respective IC; an encryption module for encrypting data communicated from the respective IC to the neighboring ICs; and a decryption module for decrypting data received from the neighboring ICs.

Abstract: Embodiments of an interposer package structure are provided herein. Embodiments include a substrate having first and second opposing surfaces. An IC die electrically coupled to the first surface of the substrate. A plurality of contact members coupled to the first surface of the substrate. An interposer having a plurality of contact elements located on a first surface. Each conductive element coupled to a respective one of the plurality of contact members.

Abstract: In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars.

Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

Abstract: An NFC-enabled device includes a load modulation communication section providing two or more selectable changes in the load impedance across the antenna terminals. At least one of the two or more selectable changes is dependent on both the transmit data arid the concurrently detected strength of a tag reader field coupled to the NFC antenna.

Abstract: Embodiments provide an area, cost, and power efficient multi-service transceiver architecture. The multi-service transceiver architecture simplifies receiver/transmitter front ends needed for a multi-service architecture, by replacing significant portions of multiple receiver and/or transmitter front ends with a single ADC and/or DAC, respectively. In embodiments, a plurality of received service contents are combined into one composite analog/RF signal and applied to an ADC. The ADC converts the composite signal into a composite multi-service digital signal. Digital techniques are then used to separate the plurality of service contents into a plurality of respective digital streams that each can be independently demodulated. Similarly, in the transmit direction, a plurality of digital streams, including a plurality of service contents, are combined into one composite digital signal.

Abstract: A signal acquisition system efficiently acquires a transmitted signal even at very low power. The system may synchronize to a preamble structure in the transmitted signal and, for example, determine timing parameters that locate the preamble with respect to system timing or other clock references. The system is particularly effective at acquiring weak power signals and is also robust against significant noise and other impairments, and therefore improves the ability of a receiving device that incorporates the signal acquisition system to acquire the signal and establish communication with other devices.

Abstract: A switching regulator arrangement utilizes internal capacitors rather than external capacitors for driving output power transistors. Low-dropout linear voltage regulators together with a dip compensation circuit provide an intermediate supply voltage for driving power transistors under circumstances in which a supply voltage is greater than a gate drive voltage of the power transistor, allowing for a more efficient absorption of transient current.