Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Abstract: A processor arrangement changes its default time interval for entering a power saving mode based sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving.

Abstract: Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be.

Abstract: Embodiments for video content source resolution detection are provided. Embodiments enable systems and methods that measure video content source resolution and that provide image-by-image source scale factor measurements to picture quality (PQ) processing modules. With the source scale factor information, PQ processing modules can be adapted dynamically (on a picture-by-picture basis) according to the source scale factor information for better picture quality enhancement. In addition, embodiments provide source resolution detection that is minimally affected by video coding artifacts and superimposed content (e.g., graphics).

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: An integrated circuit is disclosed that can be included in a host electronic device that can be commonly manufactured, where the integrated circuit can be designated (“locked”) for a specific manufacturer, thereby substantially reducing the likelihood that a third party will be able to successfully clone a host electronic device manufactured by the specific manufacturer and/or swap the chip containing the integrated circuit for one having more enabled features. The integrated circuit includes an ID module that can be programmed after fabrication. Components within the integrated circuit designate manufacturer-specific configurations (e.g., address mapping, pin routing and/or vital function releasing) based on the programmed manufacturer ID. As a result, once the integrated circuit has been programmed with the manufacturer ID, the integrated circuit will function correctly only within a host device manufactured by the manufacturer associated with the programmed manufacturer ID.

Abstract: Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.

Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Abstract: Systems and methods for partitioning memory into multiple secure and open regions are provided. The systems enable the security level of a given region to be determined without an increase in the time needed to determine the security level. Also, systems and methods for identifying secure access violations are disclosed. A secure trap module is provided for master devices in a system-on-chip. The secure trap module generates an interrupt when an access request for a transaction generates a security error.

Abstract: An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit, Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

Abstract: An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Abstract: An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

Abstract: Embodiments of the present disclosure provide systems and methods for proactively managing power in a device. A power management unit (PMU) receives information from various subsystems of a device and estimates the total power required by each subsystem of the device. Based on this information, the PMU can predict power requirements for a particular subsystem or for one or more application(s) to execute. Based on this prediction, the PMU can reconfigure the subsystems so that the device executes more efficiently given the current battery life of the device. Proactive power management advantageously gives the PMU the capability to predict power needs of various subsystems of a device so that the power supplied to these subsystems can be managed in an intelligent way before battery resources are exhausted.

Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.

Abstract: Methods and systems for processing video information are disclosed herein and may comprise calculating at least one vertical gradient of a plurality of adjacent pixels within a current field. A two-field difference may be calculated between a plurality of pixels within a first field and a corresponding plurality of pixels within a second field. At least one pixel may be deinterlaced within the current field based at least in part on the calculated at least one vertical gradient and the calculated two-field difference. The two-field difference may indicate an amount of motion between the plurality of pixels within the first field and the corresponding plurality of pixels within the second field. Phase shifting may be applied to at least one of the plurality of pixels within the first field and the corresponding plurality of pixels within the second field to effect in-phase alignment.

Abstract: A method, system and computer program product to schedule transmissions in a two-tier network are provided. In an example, the system includes a Data Over Cable Service Interface Specification (DOCSIS) scheduler configured to generate a MAP message to allocate bandwidth and a first instance in time to a cable modem to transmit data to a branch node. The system further includes a MAP message translator coupled to the DOCSIS scheduler and configured to determine a second instance in time at which data from the cable modem arrives at the branch node and generate a GATE message that grants the branch node bandwidth to transmit the data received from the cable modem at the second instance in time to a headend node.

Abstract: A semiconductor device includes a memory storing a lookup table including stored values associated with modes of operation of a component of the semiconductor device. A monitor monitors an operating parameter of the component in real-time, and reports a calculated value associated with the same. A power manager determines a change in the mode of operation of the component based on a comparison of the calculated value with a corresponding stored value, and adjusts a current mode of operation of the component in real-time.

Abstract: An apparatus for transmitting data in an xDSL system is disclosed. In an exemplary embodiment, the apparatus comprises a transmitter that sends data over an xDSL system in the form of a data transmission unit (DTU), the transmitter having physical media specific—transmission convergence (PMS-TC) communication sublayer. The apparatus may further include a retransmission unit that is implemented in the PMS-TC sublayer. The retransmission unit may include a retransmission buffer that stores and indexes transmitted DTUs in retransmit containers. The retransmit container may be defined as a time slot corresponding to a sent DTU, wherein the retransmission unit is configured to respond to a retransmission request indicating which stored DTU should be retransmitted. The stored DTU to be retransmitted may be identified by its corresponding retransmit container.

Abstract: A method and system for decoding SACCH control channels in GSM-based systems with partial combining using weighted SNR may comprise combining least one weighted bit of a GSM slow associated control channel (SACCH) frame with at least one weighted bit of a subsequent GSM SACCH block based on burst signal to noise ratios (SNRs) of the GSM SACCH block and the subsequent GSM SACCH block. The burst SNR may be determined from a mid-amble of the GSM SACCH block and its subsequent GSM SACCH block. The burst SNRs of the GSM SACCH block may be translated to a corresponding plurality of scaling factors. At least a first weighting factor may be determined from the corresponding plurality of scaling factors. At least one weighted bit of the GSM SACCH block is determined utilizing the determined first weighting factor.

Abstract: Methods and systems for robust watermark insertion and extraction for digital set-top boxes are disclosed and may include descrambling, detecting watermarking messages in a received video signal utilizing a watermark message parser, and immediately watermarking the descrambled video signal utilizing an embedded CPU. The embedded CPU may utilize code that may be signed by an authorized key, encrypted externally to the chip, decrypted, and stored in memory in a region off-limits to other processors. The video signal may be watermarked in a decompressed domain. The enabling of the watermarking may be verified utilizing a watchdog timer. The descriptors corresponding to the watermarking may be stored in memory that may be inaccessible by the main CPU. The watermark may comprise unique identifier data specific to the chip and a time stamp, and may be encrypted utilizing an on-chip combinatorial function.