Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.

Abstract: Aspects of a method and system for tunneling MACSec packets through non-MACSec-enabled nodes are provided. In this regard, aspects of the invention may be utilized for transmitting MACSec Ethernet packets over MACSec and/or non-MACSec-enabled network nodes. In one embodiment of the invention, additional header information may be inserted into a MACSec packet before transmitting the MACSec packet to a non-MACSec-enabled node. Accordingly, aspects of the invention may remove the additional header information from a packet received from a non-MACSec-enabled node to distinguish the packets comprising inserted additional header information, which may comprise a distinguishing Ethertype.

Abstract: Aspects of a system for a power amplifier with an on-package matching transformer may include a DC/DC converter that enables generation of a bias voltage level within an IC die based on an amplitude of an input signal to a PA circuit within the IC die. The bias voltage level may be applied to a transformer, which is external to the IC die but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels, derived from the bias voltage level applied to the transformer, may be applied to the PA circuit.

Abstract: A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

Abstract: A wireless communication device includes an integrated circuit (IC) and an antenna system. The IC includes a baseband processing module, a network processing module, a calibration processing module, a receiver section and a transmitter section. The network processing module establishes a wireless communication protocol and operational parameters based on the wireless communication protocol. The calibration processing module generates RF receiver calibration information based on the operational parameters and RF receive feedback and generates RF transmitter calibration information based on the operational parameters and RF transmit feedback. The receiver section provides the RF receive feedback and converts an inbound RF signal into an inbound symbol stream. The transmitter section provides the RF transmit feedback and converts an outbound symbol stream into an outbound RF signal.

Abstract: A method and related computer program product for achieving high performance I/O write rates in a redundant array using a fully recoverable communication queue stored in NVRAM on a RAID controller comprising, receiving an I/O write request from an application, determining if the I/O request is an inline write command, writing inline write commands into a command queue stored in NVRAM, notifying the application generating the I/O request of command completion and requesting the operating system for further I/Os.

Abstract: Aspects of the invention provide a method and system for coding information in a communication channel. More particularly, aspects of the invention provide an method and system for synchronous running encryption and/or encoding and corresponding decryption and decoding in a communication channel or link. Aspects of the method may include encoding and/or encrypting a first data using a first or second encoding table and/or a first or second encryption table. The method may indicate which one of the first or second encoding tables or which one of the first or second encryption tables were utilized for encoding and/or encrypting the said first data. The encoded and/or encrypted first data may subsequently be transferred downstream and decoded by synchronous decoder/decryptor using a corresponding decoding and/or decryption table. The corresponding decoding and/or decryption table may be determined based on the indicated first and/or second encoding and/or encrypting tables.

Abstract: A system provides dual use of a general purpose input/output (I/O) line. In an embodiment, the system comprises a controlling circuit having a dual purpose I/O line that is selectively operable in a serial transmit mode or an I/O mode. A first circuit that receives a serial data stream when the controlling circuit operates in the serial transmit mode is coupled to the I/O line. A second circuit that generates and transmits a signal when the controlling circuit operates in the I/O mode is also coupled to the I/O line. Finally, a third circuit is disposed between the second circuit and the I/O line. In an embodiment, when the controlling circuit operates in the serial transmit mode, the third circuit maintains the second circuit in an idle state, and when the controlling circuit operates in the I/O mode, the third circuit permits the second circuit to transmit the signal to the controlling circuit.

Abstract: Aspects of a method and system for enhancing efficiency by modulating power amplifier (PA) gain are presented. Aspects of the system may comprise a PA gain modulator that enables modification of an amplitude of a digital baseband signal. A baseband processor may enable computation of a first gain value based on the modification. The baseband processor may enable computation of a second gain value based on the first gain value. A PA may enable generation of an RF output signal based on the modified digital baseband signal and the second gain value.

Abstract: There is provided a method of testing a first device using a tester. The method includes receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further include generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data.

Abstract: Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a representative embodiment, the disk drive controller comprises a host interface, a cache buffer, and a disk drive media interface. The disk drive controller comprises the necessary circuitry to execute one or more host commands provided by a host computer. Further, the disk drive controller may facilitate the generation of the cache work queue and the disk work queue. The disk drive controller executes one or more host commands that are received through the host interface such that the cache work queue and disk work queue are employed when a read or write operation is performed.

Abstract: A transceiver device for processing a frame in a wireless local area network, where the frame is one of several frame formats, which include a high throughput frame format. The transceiver device receives a frame having a training sequence, a signal field and a data payload, and processes the training sequence to detect which signal field length of a plurality of signal field lengths was used in the received frame. With the signal field length, the device processes the signal field based upon the detected signal field length to retrieve the data payload processing information.

Abstract: A modified ranging request in a broadband communications system. The modified ranging request includes a header, a management message header attached to the header, a management message payload attached to the management message header, and a CRC attached to the management message payload. The management message header enables bandwidth requests to be made by subscriber equipment without contention. The management message header also includes state of health information on the status of a downstream transmission for enabling a central location to determine how to assign subscribers to queues in an adaptive modulation scheme.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A method for input control of multiple computing devices from a single set of input devices begins by providing, by a master input device of the single set of input devices, a connection request to the multiple computing devices via a wireless channel, wherein the connection request identifies one of the multiple computing devices. The method continues by interpreting, by each of other ones of the multiple computing devices, the connection request to determine that the connection request is not addressing the each of the other ones of the multiple computing devices. In response to the connection request, the method continues by providing, by the one of the multiple computing devices, a connection response to the master input device via the wireless channel. The method continues by providing, by the one of the multiple computing devices, a slave connection request to at least one slave input device of the single set of input devices via the wireless channel.

Abstract: Aspects of a method and system for signal phase variation detection in communication systems are presented. Aspects of the system may enable detection of phase change between a current received symbol, and one or more previous received symbols. Based on the phase change a channel estimation filter bandwidth may be selected for despreading and/or descrambling one or more subsequent received symbols. In addition, a decision may be made as to whether the subsequent received symbols are to be received based on a closed loop system, or based on an open loop system.

Abstract: A communication system is described. In one embodiment, the communication system comprises a mobile station having a transmitter to transmit packets wirelessly according to a protocol and multiple repeaters communicably coupled with the mobile station. Each of the plurality of repeaters receives one or more packets of the wirelessly transmitted packets from the mobile station. Each of the repeaters receives an indication of which of the wirelessly transmitted packets were received without errors by other repeaters and a received signal strength for those packets. The communication system also includes a switch coupled to the repeaters. Each of the repeaters forwards to the switch each packet of the wirelessly transmitted packets that each repeater had received without errors at a received signal strength higher than any other repeater.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A capacitor sharing surge protection circuit for protecting multiple ports from harmful energy surges, such as electrostatic discharge (ESD) and cable discharge events (CDE), is provided. The protection circuit includes a plurality of diodes with respective cathodes and anodes. Each anode of the plurality of diodes is coupled to one of the plurality of ports. A bypass capacitor is coupled between the cathodes of the plurality of diodes and ground. In an embodiment, a bulk capacitor is further coupled between the cathodes of the plurality of diodes and ground.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.