Abstract: A polar transmitter includes a digital processor for producing a phase correction signal and a complex modulated digital signal including a digital phase-modulated signal. The phase correction signal is added to the digital phase-modulated signal to produce a corrected digital phase signal. The corrected digital phase signal is input to a phase-locked loop (PLL) to produce an RF phase signal that tracks the phase of the digital phase-modulated signal based on the corrected digital phase signal.

Abstract: A method and system for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering are provided. A filtering mode may be selected to generate noise-reduced pixels using FIR, IIR, or a blend of FIR/IIR filtering. Blending a current pixel and an FlR-filtered current pixel may generate a first blended current pixel. The FIR filtering may be based on the current pixel, a previous collocated pixel, and a next collocated pixel. Blending the current pixel and an IIR-filtered current pixel may generate a second blended current pixel. Blending the first blended current pixel and the second blended current pixel using an adaptive blending factor may dynamically generate a filtered output pixel. The IIR filtering may be based on the current pixel and a collocated pixel of the previous second blended video image or of the previous filtered output video image.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

Abstract: A programmable antenna includes a fixed antenna element and a programmable antenna element that is tunable to one of a plurality of resonant frequencies in response to at least one antenna control signal. A programmable impedance matching network is tunable in response to at least one matching network control signal, to provide a substantially constant load impedance. A control module generates the antenna control signals and the matching network control signals, in response to a frequency selection signal.

Abstract: A channel selection canvas for display on a video display device is disclosed. The video display device can be a television, a laptop computer, or personal digital assistant device. The channel selection canvas allows a user to preview and choose video signals to be watched. The channel selection canvas displays a set of television channel video thumbnails, which can be full motion video, slow motion video or sampled video snapshots. A channel selection canvas can also display video thumbnails for security cameras, baby monitors, video phones and the like. A channel selection canvas generator that generates channel selection canvases is also disclosed. The channel selection canvas generator can reside within a television, set top box or similar video processing device.

Abstract: An apparatus, method, and system for DC offset cancellation are provided herein. For instance, the apparatus can include a first commutating mixer switch and a second commutating mixer switch. The first commutating mixer switch can have a first input port configured to receive a first differential signal and a first differential output port. The second commutating mixer switch can have a second input port configured to receive a second differential offset signal and a second differential output port. The first and second differential output ports can be coupled to one another to provide a combined differential output signal.

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second power amplifier drivers (PADs) having respective first and second non-linear phase responses. The first non-linear phase response is based on a first bias applied to the first PAD, and the second non-linear phase response is based on a second bias applied to the second PAD. The first and second PADs are coupled in parallel to provide a combined substantially linear phase response. According to an embodiment, the first and second PADs have respective first and second average input capacitances. Signal swings about the first and second biases vary the respective first and second average input capacitances, which may be combined to provide a combined average input capacitance that is substantially insensitive to the signal swings about the first and second biases.

Abstract: Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a packet network. The device may include at least one network interface to send packets to and receive packets from a data network and at least one cryptographic engine for performing encryption, decryption and/or authentication operations. The device may be configured as an in-line security processor that processes packets that pass through the device as the packets are routed to/from the data network.

Abstract: Systems and methods for providing asymmetrical cryptographic acceleration are provided. The scalable asymmetric cryptographic accelerator engine uses a layered approach based on the collaboration of firmware and hardware to perform a specific cryptographic operation. Upon receipt of a request for a cryptographic function, the system accesses a sequence of operations required to perform the requested function. A micro code sequence is prepared for each hardware operation and sent to the hardware module. The micro code sequence includes a set of load instructions, a set of data processing instructions, and a set of unload instructions. An instruction may include a register operand having a register type and a register index. Upon receipt of a load instruction, the hardware module updates size information in a content addressable memory for a register included in the instruction. The hardware module continuously monitors the content addressable memory to avoid buffer overflow or underflow conditions.

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a plurality of search engine pipeline stages, each of the plurality of search engine pipeline stages being configured to submit a particular search request to a plurality of search engines.

Abstract: Provided is a system and method for performing smart offloads between computer applications module and a network interfacing device within a data communications system. The method includes receiving data requests from the computer applications module and determining whether the received data requests require offloading. The received requests are forwarded along a first data path to the network interfacing device if offloading is required. If offloading is not required, the received data requests are forwarded along a secondary data path to a host protocol stack for processing. Next, the protocol processing is performed and the processed data requests are forwarded to the network interfacing device.

Abstract: Methods and systems for reconfigurable soft-output bit demapping, reconfigurable for different modes of operation (i.e., different transmitter/receiver configurations) and for different modulation schemes are provided. In an embodiment, a reconfigurable soft-output bit demapping system includes a mode/modulation independent equalizer, a plurality of mode/modulation independent soft-slicers coupled to the outputs of the equalizer, a plurality of mode/modulation independent post-scalers coupled to the outputs of the soft-slicers, and a mode-dependent coefficient calculator. The coefficient calculator generates parameters for configuring the equalizer, the soft-slicers, and the post-scalers according to the used mode of operation and modulation scheme.

Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Certain embodiments of a method and system for handling connection setup in a network may comprise a host that generates connection acceptance criteria and/or a services list that may be transferred to a network interface hardware device for determining whether a remote peer connection request may be accepted. The network interface hardware device may generate connection primitives to complete the network connection setup after accepting the connection request. The network interface hardware device may wait for a response from the host before generating the connection primitives. The network interface hardware device may copy the host during connection setup. The host may provide and indication to the network interface hardware device to deny the connection request or to drop the connection after the connection has been setup. The network interface hardware device may maintain a connection state generated when the connection setup is completed.

Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Abstract: Aspects of a double search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission with finite-rate channel state information feedback are provided. The method may comprise maximizing system capacity using feedback information for a plurality of signals in a frequency division duplex system to reduce a search range within which a group of signals having maximum channel gain are located. The feedback information may comprise quantized gain for the signals. Quantized channel direction for the signals within the reduced search range may be requested and received by the transmitter. One or two signals from the reduced search range that maximizes system capacity may be selected. The receivers associated with these signals may then be selected as the user group.

Abstract: A network component for processing a packet can include a buffer configured to receive a packet, a forwarding unit configured to forward the packet received at the first buffer to a loopback port, and a transmitting unit configured to transmit the packet out of the loopback port. In addition, the network component can include a loopback unit configured to loop back the packet into the loopback port, a first identification unit configured to identify an egress port, and a second transmitting unit configured to transmit the packet looped back from the loopback port out of the egress port.

Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System-On-a-Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.