Abstract: A receiver includes an antenna array that generates a plurality of received signals from at least a first remote transmitter and a second remote transmitter. Aa plurality of receiver sections process the plurality of received signals to generate a plurality of down-converted signals. A receiver processing module generates a first plurality of reception matrices corresponding to the first remote transmitter based on the plurality of down-converted signals, generates a first reception statistic from a sum based on the first plurality of reception matrices, and generates an association decision corresponding to one of: the first remote transmitter and the second remote transmitter, based on the first reception statistic.

Abstract: A receiver includes an antenna array that generates a plurality of received signals from at least a first remote transmitter and a second remote transmitter, the antenna array having a beam pattern that is controllable based on at least one control signal. A plurality of receiver sections process the plurality of received signals to generate a plurality of down-converted signals.

Abstract: A video processing system includes a video encoder that encodes a video stream into a independent video layer stream and a first dependent video layer stream based on a motion vector data or grayscale and color data.

Abstract: An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop.

Abstract: A multi-band receiver includes a first receiver coupled to receive a first desired signal component of an RF signal over a first range of frequencies and generate a first received signal. A second receiver receives a second desired signal component of the RF signal over a second range of frequencies and generates a second received signal. The second receiver includes a harmonic cancellation module that attenuates a harmonic of the first desired signal component that falls within the second range of frequencies.

Abstract: A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A method for decoding bi-phase encoded data begins by interpreting a first bit boundary of a bit of the bi-phase encoded data to produce a first boundary value. The method continues by interpreting a second bit boundary of the bit of the bi-phase encoded data to produce a second boundary value. The method continues by comparing the first boundary value to the second boundary value to produce a decoded bit.

Abstract: According to one exemplary embodiment, a power supply rejection bias circuit includes a first amplifier coupled to a second amplifier, where the first amplifier receives a reference voltage, and a feedback voltage of the bias circuit. The bias circuit further includes an output transistor driven by the output of the second amplifier, where the output transistor provides the output of the bias circuit and the feedback voltage. The bias circuit further includes a feedback resistor coupled between an input and an output of the second amplifier. According to this embodiment, the output of the second amplifier forms a non-dominant pole of the bias circuit and the output of the bias circuit forms a dominant pole of the bias circuit, thereby increasing power supply rejection of the bias circuit.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to determine equalizer coefficients for a composite signal that includes a first information signal and a second information signal. First and second information signal channel estimates and channel powers based upon training symbols are determined. A composite signal power is determined. A noise variance of the composite signal is determined based upon the first information signal channel power, the second information signal channel power, and the composite signal power. A plurality of equalizer coefficients are determined based upon the first information signal channel estimate, the second information signal channel estimate, and the noise variance of the composite signal.

Abstract: A voice, data and RF integrated circuit includes a processing module that generates at least one control signal that indicates a receive calibration mode. An RF transmitter generates a transmit signal that includes a first calibration signal when the at least one control signal indicates the receive calibration mode. An RF receiver receives a received signal that includes the first calibration signal and generates at least one receiver equalization parameter for equalizing the RF receiver in response to receiver feedback signals, when the at least one control signal indicates the receive calibration mode.

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract: In a wireless communication system, a method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a cipher key parameter and a key modifier. A number of processing blocks of output bits may be determined based on a number of bits in an output keystream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the processing block of output bits being processed. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available and may be grouped into two final blocks of output bits in the output keystream.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method for supporting communication between a source internet protocol phone and a destination internet protocol phone is provided. The source internet protocol phone communicates via a Network Address Translator (“NAT”) gateway. The method includes receiving a packet from the source phone at the NAT. The packet is for communication with the destination phone. The method further includes querying whether the destination phone is located in the subnetwork serviced by the NAT gateway. If the destination phone is not located in the subnetwork serviced by the NAT gateway, then the method includes sending the packet upstream to the destination phone via the Internet. If the destination phone is located in the subnetwork serviced by the NAT gateway, then the method includes directing the packet to the destination phone.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning a local oscillation frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Abstract: A baseband processing module according to the present invention includes a multi-path scanner module. The multi-path scanner module is operable to receive timing and scrambling code information regarding an expected multi-path signal component of a WCDMA signal. Then, the multi-path scanner module is operable to identify a plurality of multi-path signal components of the WCDMA signal by descrambling, despreading and correlating a known symbol pattern of/with a baseband RX signal within a search window. The multi-path scanner module is operable to determine timing information for the plurality of multi-path signal components of the WCDMA signal found within the search window and to pass this information to a coupled rake receiver combiner module.

Abstract: An RF front-end includes a transmit adjust module, a PA module, an antenna coupling circuit, a LNA module, and a receive adjust module. The transmit adjust module adjusts coordinates of up-converted analog signals when in a first transmit mode and adjusts coordinates of a plurality of up-converted analog signals when in a second transmit mode to produce to produce multiple adjusted up-converted signals and a plurality of adjusted up-converted signals, respectively, which are subsequently amplified by the PA module. The antenna coupling circuit provides the multiple or the plurality of outbound RF signals to at least some of a plurality of antennas depending on the transmit mode and provides multiple or a plurality of inbound RF signals at least some of the plurality of antennas to the LNA module based on a receive mode. The receive adjust module adjusts coordinates of the multiple or plurality of amplified inbound RF signals based on the receive mode.