Abstract: A mesh grid protection system is provided. The protection system includes a plurality of grid lines forming a mesh grid proximate to operational logic. The protection system also includes tamper-detection logic coupled to the plurality of grid lines and configured to toggle a polarity of a signal on at least one grid line at each clock cycle and to detect attempts to access the operational logic by comparing a reference signal driving a first end of a grid line to a signal at the opposite end of the grid line.

Abstract: The present invention is directed to a system for demultiplexing video signals that have been combined using a time division multiplexing approach. The system includes synchronizers, parsers, demultiplexers, and an input buffer. Each demultiplexer within the system includes a header detect module, a slot map module, a frame sync module and a packet accept module. The method includes the steps of receiving an input stream that contains data packets for more than one program channel that have been combined in which packet identification (PID) information is used and a time division multiplexing scheme, such as transport stream multiplexing format (TSMF) is used. The PID and slot location for each packet is analyzed. Based on the PID and slot location a packet is either accepted or rejected.

Abstract: A dual band antenna includes a far field antenna structure for facilitating the communication of first data with a remote device via far field signaling in a millimeter wave band. A near field antenna structure facilitates the communication of second data with a remote device via near field signaling in a near field band. The far field antenna structure and the near field antenna structure share at least one common antenna element.

Abstract: Aspects of a method and system for a single antenna receiver system for HSDPA are provided. Aspects of a method for processing RF signals, the method may comprise computing channel estimates based on a plurality of received individual distinct path signals, generating timing reference signals indicating a location of at least one of the plurality of received individual distinct path signals, combining at least a portion of the plurality of received individual distinct path signals as a signal cluster based on at least one of the computed channel estimates and said generated timing reference signals, and selecting at least one of combining and equalization processing based on at least one of the computed channel estimates and the generated timing reference signals. Aspects of a system for processing RF signals may comprise circuitry that selects at least one of combining and equalization processing based the computed channel estimates and/or generated timing reference signals.

Abstract: A method and system for improving a level of service between wireless devices. Handheld devices implementing the Bluetooth specification typically have relatively limited transmission ranges. As a result, and since they are typically portable, such devices easily experience abrupt communication interruptions, either between themselves and other handheld devices, or between themselves and fixed devices. The effective range of the devices can be extended by providing additional error-correcting coding. Although this modification also results in an extended transmission time, users are provided with an increased transmission range, and are given warning that service may soon be interrupted. Users may then, if they wish, take such steps as finishing their communication or moving into their devices' normal transmission range. Additionally, the handheld devices may use the extra transmission time and range to search for a forwarding path to a recipient device, thus minimizing or preventing any service interruption.

Abstract: A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.

Abstract: Methods and systems for processing a video signal are disclosed herein. Pixels may be interpolated utilizing at most two passes. During a first of the two passes, an aligned sub-pixel value may be interpolated utilizing a plurality of integer pixel values, if the aligned sub-pixel value is horizontally or vertically aligned with the plurality of integer pixel values. During a second of the two passes, a non-aligned sub-pixel value may be interpolated utilizing the interpolated aligned sub-pixel value, if the non-aligned sub-pixel value is not horizontally or vertically aligned with the plurality of integer pixel values. The aligned sub-pixel value may be interpolated utilizing 4-tap filtering of the integer pixel values.

Abstract: Methods and systems for processing signals for a multiband radio are disclosed herein. Aspects of the method may comprise dividing an input signal generated by an oscillator used to generate signals for each of a plurality of bands for the multiband radio. A feedback loop reference signal may be generated from the input signal and a coarse calibration signal may be generated from the feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal. The input signal may be buffered and/or divided by a divide by four (4) divider circuit. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The generated feedback loop reference signal may be buffered and/or divided prior to the calibration. The coarse calibration signal may comprise a 7-bit calibration signal. A fine calibration signal may be generated from the feedback loop reference signal.

Abstract: This invention provides colored noise detection algorithm(s). This colored noise detection algorithm(s) may be implemented with a multi-branch equalizer processing module that enables interference cancellation when colored noise is associated with received radio frequency (RF) bursts. The noise discriminator identifies when the radio frequency (RF) bursts have white noise or colored noise associated with them. Alternatively the noise discriminator may be able to determine and enable interference cancellation in response to an interference-limited received RF burst as opposed to a noise-limited received RF burst. The multi-branch equalizer improves the signal-to-noise ratio by improving the equalization with a second branch operable to be trained based upon known training sequences and at least partially re-encoded data bits.

Abstract: A power detector having temperature compensation for improved measurement performance includes a pair of rectifier transistors coupled to a differential input signal biased by a first temperature dependent current. An output of the pair of rectifier transistors provides a first component of a differential DC output signal. The first component of the differential DC output signal includes a DC voltage proportional to an amplitude of the differential input signal plus an offset voltage. The power detector further includes a reference transistor biased by a reference current. The reference current includes a second temperature dependent current and a temperature independent offset current for temperature compensation. An output of the reference transistor provides a second component of the differential DC output signal that includes a reference voltage.

Abstract: An integrated circuit radio transceiver and method therefor comprises circuitry that is operable to up-convert an outgoing continuous waveform signal to RF and that is further operable to down-convert and ingoing RF signal to one of a baseband or intermediate frequency in a manner that provides a linearized output current having an amplified current magnitude for mixing with a local oscillation in a mixer block. Specifically, a circuit portion is operable to produce a linearized current based upon an input signal. The linearized current is then produced to a current mirror block that produces a scaled and amplified output current. The scaled and amplified output current is then produced to a mixer block for mixing with a local oscillation to create the outgoing RF signal or the ingoing baseband or intermediate frequency signal.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: A system and method for block-based per-pixel correction for film-based sources. The appearance of mixed film/video can be improved through an adaptive selection of normal deinterlaced video relative to inverse telecine video. This adaptive selection process is based on pixel difference measures of sub-blocks within defined blocks of pixels.

Abstract: A system and method for secure communication for power over Ethernet (PoE) between a computing device and a switch. Various power management information can be used as inputs in a process for determining a power request/priority. This power management information can be communicated in Layer 2, Layer 3, or higher messaging during initial power allocation and ongoing power reallocation. Encryption of such messaging enables confidentiality, secure allocation processes, and prevention of denial of service attacks.

Abstract: A method performs automated at-speed testing of devices. The method includes the steps of generating multiplexer control signals, forming various signal paths between a set of multiplexers and the devices based on the multiplexer control signals, and routing test signals having multiple gigabit per second (MGBPS) baud rates through the signal paths.

Abstract: A system and method for providing increased manufacturing yield for integrated circuits. Various aspects of the invention may comprise receiving an integrated circuit designed to operate at nominal power supply characteristics. The integrated circuit may, for example, be tested at nominal power supply characteristics to determine if the integrated circuit meets performance requirements at nominal power supply characteristics. If the integrated circuit meets performance requirements at nominal power supply characteristics, then the integrated circuit may designated as such and further processed accordingly. Such a designation may, for example be visible, electronic or procedural. Various aspects of the present invention may also comprise testing the integrated circuit at non-nominal power supply characteristics to determine if the integrated circuit meets performance requirements at non-nominal power supply characteristics.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.