Abstract: A modulation control module for use in an RF transceiver, the modulation control module includes a processing module and memory. The memory is operably coupled to the processing module, wherein the memory stores operational instructions that causes the processing module to: receive a multiple path channel estimation; and determining, for each transmit path of a multiple input multiple output (MIMO) wireless communication, a modulation control signal based on a corresponding portion of the multiple path channel estimation.

Abstract: Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine can be decoupled from surrounding logic by using asynchronous buffers. Bit-sliced design can be implemented by moving expansion and permutation logic out of the timing critical data path. An XOR function can be decomposed into functions that can be implemented more efficiently. A two-level multiplexer can be used to preserve a clock cycle during cryptography processing. Key scheduling can be pipelined to allow efficient round key generation.

Abstract: Certain aspects of the invention for producing a secure key may comprise a secure key generator that receives a first, second and third input keys and utilizes these keys to generate a first output key. The first, second and third input keys may be a customer key, customer key selection and key variation, respectively. The first output key may be generated so that it is unique, differs from the first input key and is not a weak or semi-weak key. The first, second and third input keys may be mapped to generate mapped output key data and an intermediate key generated based on the first input key. The intermediate key and the output key data may be scrambled to create a scrambled output. At least a portion of the output key data may be masked and XORed with the scrambled output to generate the first output key.

Abstract: A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital sample values at a relatively higher sampling rate than the sampling rate of the digitized input samples, each higher sampling rate sample having fewer bits than the original samples. The higher sampling rate stream is then distributed for sequential conversion by multiple digital-to-analog converters each operating at a lower sampling rate. The outputs of the converters are then combined to form a combined output signal. Most spectral images normally observed in a standard or conventional DAC are attenuated in the combined output signal of an embodiment in accordance with the present invention. Any spectral images that remain are further from the signal of interest, permitting the use of lower cost filtering.

Abstract: A signal weighting and combining method implemented within a receiver having a plurality of receive antennas is disclosed herein. Each receive antenna is disposed to produce a received RF signal in response to a transmitted RF signal received through a channel. The method includes weighting the plurality of received RF signals produced by the antennas in accordance with a corresponding plurality of RF weighting values selected to minimize an output bit error rate of the receiver, thereby forming a plurality of weighted RF signals. The method further includes combining ones of the plurality of weighted RF signals in order to form one or more combined RF signals. A similar splitting and weighting method capable of being implemented within a transmitter having a plurality of transmit antennas is also disclosed.

Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first and/or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first and/or the second component of the input signal. The example circuit also includes a power supply that provides a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.

Abstract: Ball grid array (BGA) packages are provided. A BGA package includes a substrate that has a surface and a stiffener that has a surface and a protruding portion. The surface of the substrate has an opening therein. The protruding portion is located on the surface of the stiffener. The surface of the stiffener is coupled to the surface of the substrate. The protruding portion extends through the opening. An area of the surface of the stiffener is less than an area of the surface of the substrate. A surface of the protruding portion is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB.

Abstract: A system and method for pre-detection in a power over Ethernet (PoE) system. A power sourcing equipment (PSE) is designed to measure a port voltage upon application of a small current source. A microcontroller controls the current source based on a comparison of the measured port voltage to a threshold voltage.

Abstract: Methods and systems are provided for the secure entry and maintenance of data entered via a user input device. A computing device includes a secure processor coupled to one or more user devices. The user devices may be peripheral devices coupled to the secure processor via a wired connection such as a USB or PS/2 interface or via a wireless connection such as Bluetooth. A security boundary associated with the secure processor is established using hardware or cryptographic techniques. Input data received from the user device is stored within the security boundary. Additionally, the secure processor is configured to identify the user peripheral device coupled to the secure processor and to determine whether a request received to access the user peripheral device is allowable based on security policies defined for the user peripheral device.

Abstract: In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.

Abstract: A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.

Abstract: A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

Abstract: A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.

Abstract: A system, method and computer program product is provided that allows an end user to monitor and/or control various data streams appearing on one or more customer premises equipment (CPE) interfaces of a residential gateway, even where the data streams are of different types such as voice, video or computer data. The invention provides a user interface, implemented as part of a CPE device or as a stand-alone device, that is accessed by an end user to transmit commands to a residential gateway. A processor within the residential gateway executes gateway monitoring and control software that receives the commands and, in response, performs the necessary routing and conversion of data streams to execute the desired monitoring and/or control functions.

Abstract: Methods and systems for higher power PoE are provided. Embodiments overcome system limitations to PSE power scaling by using an endspan-midspan configuration which allocates power to the PD from both an endspan PSE and a midspan PSE. Embodiments are particularly suitable for deployed PoE systems having limited power supplies and/or ports designed for lower power. Further, embodiments include power management schemes to enable the proposed endspan-midspan configuration to intelligently allocate power between the endspan PSE and the midspan PSE according to required PD power.

Abstract: A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch having N component switches that are digitally controlled. The voltage supply interface replaces a conventional sense resistor with a calibration circuit that has a replica switch that is a replica of the N component switches. The calibration circuit includes a reference current IREF that is sourced through the replica switch. A voltage comparator forces a common voltage drop across the replica switch and the n-of-N activated component switches so that the cumulative current draw through the segmented switch is n·IREF. The current control of the voltage interface can be coarsely tuned by activating or deactivating component switches, and can be finely tuned by adjusting the reference current. The current sense resistor is eliminated so that the overall series resistance is lower.

Abstract: The present invention is directed to systems and method of controlling clock signals during scan testing integrated circuits. The methods and systems provide efficient at-speed scan testing while minimizing the external pins on an integrated circuit dedicated to scan testing clock sources. A clock control circuit is disclosed that includes a scan test control module for permitting a clock signal to be transmitted and a scan test clock decision module for determining whether a clock signal should be permitted to be transmitted. An integrated circuit is disclosed that includes a set of clock control circuits. Embodiments of a scan test control module are provided that can process decoder inputs, ATPG inputs or both. A method is provided that can be used, for example, by an ATPG tool to efficiently provided at-speed scan testing while minimizing external pins dedicated to scan testing clock sources.

Abstract: An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die area is utilized as compared to metal fuses. Additionally, because OTP memories can be implemented as part of standard complementary metal oxide semiconductor (CMOS) processes, the method is less costly and complex than the use of electrically-erasable programmable read-only memories (E2PROMs).