Abstract: A communication system and method are described. In one embodiment, the method comprises a switch receiving information from at least one repeater for each packet received without errors by the at least one repeater, the switch, in response to the information, determining an amount of wireless communication activity each of the at least one repeater is experiencing, the switch determining whether to cause one or more repeaters to change status regarding wireless reception and transmission of packets from other devices in the network based on repeater location and repeater density and the information received from the at least one repeater, and the switch causing a change in the status for at least one of the one or more repeaters by signaling to the at least one of the one or more repeaters.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

Abstract: A method and system for flexible FM tuning are provided and may include tuning to a particular frequency within a range of FM channels based on an IF frequency that includes an integer multiple of the channel spacing between neighboring allocated FM channels within the range of FM channels, offset by at most one-half the channel spacing. The method may further include determining whether the particular frequency comprises an on frequency channel, utilizing a frequency error that is based on the IF frequency. A local oscillator frequency may be selected for the tuning based on the frequency offset. An intermediate frequency (IF) channel may be generated utilizing the particular frequency and the selected local oscillator frequency. The generated IF channel may be between neighboring channels selected from the range of FM channels. The frequency error may be determined for the particular frequency within the range of FM channels.

Abstract: LDPC (Low Density Parity Check) coded 128 DSQ (Double Square QAM) constellation modulation and its associated labeling. A novel means is introduced by which a constellation may be arranged and mapping in its symbols may be determined to provide for improved performance. One application area in which this may be employed is transmission over twisted pair (typically copper) cabling existent within data centers of various networks. The operation of the IEEE 802.3 Ethernet local area networks currently being used (as well as those currently under development) would benefit greatly by employing the various principles presented herein. When this novel approach of an LDPC coded 128 DSQ constellation modulation combined with TH (Tomlinson-Harashima) preceding is employed within a communication device at a transmitter end of a communication channel (i.e., in a transmitter and/or a transceiver), the overall operation of a communication system may improve significantly when compared to prior techniques.

Abstract: Aspects of a greedy search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission with finite-rate channel state information feedback are provided. The method may comprise receiving feedback information via a communication channel for a plurality of users in a frequency division duplex system. The system capacity may be maximized using the feedback information based on a signal from a single user within a reduced search range or based on the signal from the single user and at least one other signal from another user within a remaining portion of the search range. The feedback information may comprise quantized gain and/or direction of the channel state information of the users.

Abstract: Systems and methods that provide channel-adaptive antenna selection in multi-antenna-element communication systems are provided. In one embodiment, a method that selects a subset of receive antennas of a receiver to receive a transmitted RF signal may include, for example, one or more of the following: establishing possible subsets of the receive antennas; determining sets of channel parameter statistics corresponding to the possible subsets of the receive antennas; computing output bit error rates of the receiver, each output bit error rate being computed based on at least one set of channel parameter statistics; selecting a particular possible subset of the receive antennas based upon a criterion predicated on the computed output bit error rates; and connecting one or more RF chains of the receiver to the receive antennas of the selected particular possible subset.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, either copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

Abstract: Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: Carrier frequency offset (CFO) estimation from preamble symbols. Any communication receiver may be adapted to perform the CFO estimation. The CFO estimation is performed using a low complexity, high accuracy CFO estimation method. The operation may be described as follows: each element of a received sequence is divided by the corresponding preamble element, the resulting sequence is divided into N subgroups, and each subgroup is then averaged. The phase differential of the resulting sequence is computed, averaged, and used to compute an estimate of the carrier frequency offset. This approach to performing CFO estimation is of relatively high estimation accuracy and of relatively low computational complexity.

Abstract: A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage devices from being accessed by the operating system, and selectively revealing one or more of said hidden storage devices as needed to permit access to the information stored therein.

Abstract: A system and method relieves ESD requirements on devices in circuits of chips that are susceptible to being damaged from ESD through an external pad. For example, one of the devices can be NMOS transistors having drains (or sources) connected to the external pad(s) and no (or significantly small) current flows from their drains (or sources) to the corresponding pad(s). In order to protect such a device, an ESD protecting system is coupled between the NMOS device and the pad. The ESD protecting system can include an n-type transistor or a p-type transistor.

Abstract: A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric performs error detection operations, and extracts information from a MAC packet that it produces.

Abstract: In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource.

Abstract: Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.

Abstract: The present invention provides systems and methods for pseudo-random signal generation in a multi-carrier communications system. In embodiments, a transmitter includes a pseudo-random bit sequence (PRBS) generator and Medley signal generator. The PRBS generator can operate in at least one of the following modes: a parameter selection mode, a scrambler mode, and/or a combination mode. The Medley signal generator receives an output bit sequence from the PRBS generator. The Medley signal generator then generates a Medley signal which includes a set of Medley tones encoded based on the output bit sequence from the PRBS generator. The Medley signal is then sent over channels of a multi-carrier communication system such as an ADSL system.

Abstract: A network device for processing a packet can include an ingress port configured to receive the packet. In addition, the network device can include a membership port bit map table configured to store at least one membership port bit map, an outgoing port bit map table configured to store at least one outgoing port bit map. A first storage unit within the network device can be configured to store an egress port bit map. The egress port bit map is based on the membership port bit map and the outgoing port bit map. Furthermore, the network device can have at least one egress port configured to transmit out the packet. The at least one egress port can correspond to the egress port bit map.

Abstract: A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) to provide a plurality of gain steps thereby providing automatic gain control (AGC) in a receiver intermediate frequency (IF) stage comprising a succession of operational amplifiers wherein at least one is for providing fine gain control and wherein the gain of each fine gain amplifier is controlled by the resistance ratios of a plurality of selectively biased MOSFETs. In one embodiment of the invention, three coarse amplifiers are provided, each having a gain of either 0 dB or 12 dB based on the value of a two-state signal provided to each amplifier gain control input. A single fine gain amplifier has a gain of 0 dB, 3 dB, 6 dB or 9 dB based on the binary value of the two-bit signal provided to the amplifier.

Abstract: Methods and systems for processing a packet are disclosed herein. Aspects of the method may comprise replicating at least one component of a legacy preamble synchronization symbol to generate a plurality of replicated components of a legacy preamble synchronization symbol. A portion of the generated plurality of replicated components of a legacy preamble synchronization symbol may be grouped and scaled to at least one wide-bandwidth synchronization symbol. A wide-bandwidth preamble may be generated utilizing the wide-bandwidth synchronization symbol. The replicated component of the legacy preamble synchronization symbol may comprise a time domain component and/or a frequency domain component. The time domain component may comprise at least one modulated symbol and the frequency domain component may comprise at least one tone.