Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: In an RF communication system, aspects for supporting cellular or wireless network and broadcast utilizing an integrated single chip cellular and broadcast silicon solution may comprise receiving in a mobile terminal, a plurality of cellular frequency band communications services and VHF/UHF band broadcast services in a single baseband processor IC within a mobile terminal. Cellular information associated with the cellular frequency band communications service, and VHF/UHF broadcast information associated with the VHF/UHF broadcast service may be processed by a cellular processing module and a VHF/UHF broadcast processing module, respectively, integrated within a single integrated circuit within the mobile terminal. The cellular processing module and the VHF/UHF broadcast processing module within the mobile terminal may operate independently of each other to separately process the cellular information and the VHF/UHF broadcast information without exchanging related information.

Abstract: A method and apparatus for accessing, controlling and utilizing a network communication medium. Various aspects of the present invention may comprise a first networked device with power-save capability. The first networked device may acquire control of a communication medium utilizing a medium access protocol, which may be contention-based. The first networked device may utilize the communication medium to communicate information to a second networked device. The first networked device may transfer control of the communication medium to the second networked device, whereby the second networked device may control the communication medium without having to acquire control of the communication medium by utilizing the medium access protocol. The second networked device may utilize the communication medium to communicate information to the first networked device while maintaining control over the communication medium.

Abstract: A system and method for accelerated performance of quadrature amplitude modulation (QAM) is provided. The system includes multiple general purpose registers and multiple execution units configured to decode a set of QAM tones in parallel or an individual QAM tone in response to a single instruction executable by the processor. Each of the plurality of execution units is configured to decode one of the set of QAM tones according to a constellation size associated with the one of the set of QAM tones. The QAM decoding method includes reading a constellation size value for each of a set of received input tones. For each tone in the set of input tones, an ideal point in a QAM constellation of the associated constellation size closest to the X and Y coordinates of the tone is determined. The data values of the ideal points are then stored in a destination register.

Abstract: A video processing system captures a sequence of original video frames with a video camera, presents at least one frame of the sequence of original video frames on a video display, receives user input regarding the sequence of original video frames, and presents a sub-frame on the video display that corresponds to a region in at least one frame of the sequence of original video frames that is identified in the user input. The video processing system also generates metadata corresponding to the sub-frame, the metadata to be used by a target video player in modifying the sequence of original video frames to produce a full screen presentation on a target video display of the target video player corresponding to the sub-frame. Targeted sub-frame metadata can be specifically generated for use with a particular screen or screen size.

Abstract: In a digital communication infrastructure, intermediate network nodes compare packets from end-point devices with pluralities of virus templates. Upon detecting matches, virus service functions are invoked which interrupt the packet flow. Network wide template and service functionality updating is provided to service pluralities of virus service software vendors. Non-repetitive detection processing minimizes network load. Virus service functions may execute locally and/or remotely. Servicing may include dropping packets containing virus codes or, processing and routing the packets. Pop-up messages revealing underlying template matches are delivered with human challenge mechanism. The network nodes may be routers, packet switching exchanges, switches, access points, Internet service provider equipment, etc. External vendor servers and server clusters may assist network nodes in detecting and processing packets for virus codes.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract: Video player circuitry used with encoded source video and a display. Decoder circuitry receives encoded source video and decodes the encoded source video to produce a sequence of full frames of video data. Pre-processing circuitry, pursuant to sub-frame information, generates a plurality of sequences of sub-frames of video data from the sequence of full frames of video data, a first sequence of the plurality of sequences of sub-frames of video data having a different center point within the sequence of full frames of video data than that of a second sequence of the plurality of sequences of sub-frames of video data. Post-processing circuitry, pursuant to supplemental information, modifies the plurality of sequences of sub-frames of video data to produce an output. Interface circuitry that delivers the output for subsequent presentation on the display.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to the operational section. The I/O section comprises a transformer and a switching device. The transformer includes a primary side connected to first and second I/O ports and a secondary side connected to the operational section. The switching device is coupled to the controller and between the first and second I/O ports and a bias port, such that, under control of the controller, the switching device connects one of the first and second I/O ports to the bias port.

Abstract: A method, system, and computer program product for ordering grants of upstream bandwidth in a two-way grant-based communication system, such as a DOCSIS-based communication system. Typically, a central controller, such as a CMTS, sends a grant message to a set of end user devices, e.g., cable modems, wherein the message defines when each end user device can transmit upstream. The invention first determines, for each end user device, the time needed for processing the grant message. The central controller then constructs the grant message, such that grants for the end user devices associated with the shortest grant message processing times occur early in the grant message and represent the earliest grants. Grants for end user devices associated with the longest grant message processing times occur later in the grant message and represent later grants.

Abstract: Virtual disk drive architecture. A novel approach is presented by which a virtual design system allows for the design, development, and testing of memory storage devices including hard disk drives (HDDs). A virtual disk drive architecture allows for the implementation and emulation of a full HDD system. All of the pieces of the HDD system (e.g., including both the read channel and the controller functionalities) are included and implemented to allow a designer to develop and test certain portions within the system. In some embodiments, one or more field programmable gate arrays (FPGAs) are employed to implement a hard drive (HD) controller in an all digital implementation. Various combinations including circuit boards and FPGAs can be employed to emulate an entire HDD system. In even other embodiments, one or more sockets, and appropriate interfacing, are included to allow the testing of actual chips within the virtual disk drive architecture.

Abstract: Upstream requests such a bandwidth requests, are processed by CMTS out of order on a priority basis to reduce latency in responding to the request. Specifically, a cable modem termination system (CMTS) is connected to a plurality of cable modems by a cable plant. The CMTS has a burst receiver adapted to be connected to the cable plant to process upstream data packet units and bandwidth requests transmitted by the cable modems. Each packet includes a header that uniquely distinguishes the bandwidth requests from other data types. Packet data units are arranged in a first memory queue. Bandwidth requests are arranged in a second memory queue. The headers of the packets processed by the burst receiver are inspected as they arrive at the CMTS to determine if the packets are packet data units or bandwidth requests. Packet data units are routed to the first memory queue. Bandwidth requests are routed to the second memory queue.

Abstract: Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

Abstract: A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second operating states of the wireless interface unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having low phase-noise characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication system may include generating a first digital signal from a received analog signal bearing communicated information, the first digital signal having a pre-cursor response and a post-cursor response. A second digital signal may be generated that limits a duration of at least a portion of the post-cursor response and a third digital signal may be generated that inhibits at least a portion of the pre-cursor response. A fourth digital signal that inhibits at least a portion of the post-cursor response and a fifth digital signal that limits a duration of at least a portion of the fourth signal may be generated in order to recover the communicated information. A sixth digital signal based on at least the third digital signal and the fifth digital signal may be generated.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.