Abstract: A radio frequency (RF) tuner includes a programmable tracking filter bank receiving an RF input and outputting a filtered RF signal. A mixer stage receives the filtered RF signal and outputs a first quadrature component of the filtered RF signal and a second quadrature component of the filtered RF signal. Two variable gain amplifiers receive the first and second quadrature components and output amplitude-controlled I and Q components of the filtered RF signal. In one embodiment, the programmable tracking filter bank includes a plurality of tank circuits each connected to the RF input through an impedance. Each tank circuit include an inductor and a capacitor connected in parallel thereby forming an LC network, and a plurality of switched capacitors in parallel with the LC network and switched in and out of the tank circuit by programmable switches. In another embodiment, the programmable tracking filter bank includes a plurality of peaked low-pass circuits each connected to the RF input through an impedance.

Abstract: A video and graphics system provides square graphics pixels to blend images having 640×480 pixels, such as graphics images provided by some set top boxes and intended to be displayed at a 12.27 MHz display sample rate, with images having 704×480 pixels, such as ITU-R 601 compliant images such as NTSC SDTV images, having oblong pixels and displayed at a 13.5 MHz display sample rate. A sample rate converter including a multi-phase-multi-tap filter is used to generate square pixels. The multi-phase-multi-tap filter provides a good balance of sharpness, smoothness, anti-aliasing and reduced ringing. The multi-phase-multi-tap filter can also be used to convert images having 320×480 pixels to images having 704×480 pixels. The multi-tap filter can be used for scan rate conversion of graphics or video images for HDTV or SDTV applications.

Abstract: A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

Abstract: A circuit includes at least two transistors arranged to form a current mirror, at least two transistors operatively coupled to the current mirror, where the transistors are arranged to form a differential pair amplifier, and a follower transistor operatively coupled to the current mirror and to the differential pair. The transistors of the differential pair, the current mirror, and the follower transistor are operatively coupled such that during operation an amplitude of a signal output from the follower transistor is proportional to an amplitude of an signal input into the differential pair.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A method to transmit data using a device having a plurality of physical input/output (I/O) interfaces is provided. The method comprises receiving data and determining a topology according to which data is to be transmitted. Data is transmitted in sequential order via a single physical interface for a first topology and in random order via a plurality of physical interfaces for a second topology. A System On Chip (SOC) unit enabled to transmit data via one or more physical interfaces is provided. The SOC comprises a processor and a network interface including multiple physical input/output (I/O) interfaces coupled to the processor. In response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a first topology or select multiple physical I/O interfaces for random order data transmission according to a second topology.

Abstract: A system, method, and computer program product for allowing a first processor to access flash or other non-volatile memory that is associated with a second processor. The first processor obtains parameters that allow the initialization of an internet protocol (IP) stack. The parameters can be obtained using the trivial file transfer protocol (TFTP), for example. The first processor communicates with the second processor using a socket protocol, sending a command word that represents either a read or write command. The command word specifies where in the non-volatile memory the access is to occur, and for how many bytes. Information is then returned to the first processor, allowing the first processor to verify the success of the access.

Abstract: A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet from the data provider. Then, bandwidth is allocated to the data provider, where the allocated bandwidth is less than the requested bandwidth. Next, the present invention receives part of the data packet in the allocated bandwidth from the data provider, where the part of the data packet includes a fragment header, and the fragment header includes a sequence number for the part of the data packet. The part of the data packet is then stored in external memory. Finally, the data packet is reassembled by concatenating in the correct sequence the part of the data packet with other parts of the data packets to create the reassembled data packet.

Abstract: A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput.

Abstract: Methods and systems for enabling coexistence of multiple potentially interfering wireless components in a device are provided. A device may include a wireless module using a proprietary protocol and one or more modules using standardized protocols. The device further includes a coexistence arbitration module configured to arbitrate access to a shared communication medium among the wireless modules based on assertion of medium access requests by the modules and the associated priority of the asserted medium access requests. When multiple medium access requests have the same priority, precedence for access to the shared medium is determined based on additional criteria. The coexistence arbitration module may be a separate module or may be integrated into another module or distributed among the modules. The device may include a host processor for altering transmission characteristics of a module to increase the likelihood that another module can receive data within a reasonable time period.

Abstract: Methods and systems for improved lookup table mechanism for Huffman decoding are provided and may include selecting, based on a plurality of entropy encoded bits from a received bitstream, one of a plurality of codewords that is indexed according to a specific length and that points to all entries which include the specific length. The plurality of entropy encoded bits from the received bitstream may be matched with at least one of the entries that include the specific length. The entries that include the specific length may be stored in a table in memory. A value of the plurality of entropy encoded bits may be compared with the selected one of the plurality of codewords that is indexed according to specific length. The plurality of entropy encoded bits from the received bitstream may be decoded based on the matched at least one of the entries comprising the specific length.

Abstract: One or more methods and systems to efficiently process MPEG video in order to perform a reverse play or slow rewind function are presented. The method reduces system bandwidth required to implement the reverse play function when SD MPEG video is received by the MPEG decoder. Furthermore, the method maximizes the use of memory resources when one or more video frame buffers are implemented. The system comprises a first subsystem feeding one or more sequences of frames (e.g., feeding sessions) to a second subsystem. The first subsystem defines a set of parameters that is used to determine the one or more feeding sessions provided to the second subsystem. The second subsystem subsequently decodes the one or more feeding sessions using the set of parameters such that the video may be displayed.

Abstract: A method is disclosed for maintaining the integrity of a communication system. The method comprises detecting common path distortion (CPD) and periodic impulse/burst (PIB) noise in a received signal in the communication system. After isolating the CPD and PIB noise, ingress noise in the received signal is identified. Isolating the CPD and PIB noise thus prevents improper classification of CPD and PIB noise as ingress noise. Operating parameters of the communication system are then adapted in accordance with the identified ingress noise, the detected CPD and/or the detected PIB noise.

Abstract: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Abstract: A wireless terminal operates within a Wireless Local Area Network (WLAN) and includes a directional antenna, a radio frequency unit operably coupled to the directional antenna, and a processor operably coupled to the radio frequency unit. The processor controls the operation of the wireless terminal to operate within the WLAN to assist in WLAN service management. In its operations, the wireless terminal listens to a plurality of beacons transmitted by a corresponding plurality of Wireless Access Points (WAPs) of the WLAN. The wireless terminal then characterizes the plurality of beacons with regard to signal quality. Based upon the characterization, the wireless terminal selects a desired WAP of the plurality of WAPs. The wireless terminal then associates with the desired WAP of the plurality of WAPs. Finally, the wireless terminal adjusts a gain vector of a servicing antenna of the wireless terminal so that it is substantially directed toward the desired WAP of the plurality of WAPs.

Abstract: A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error correction code generation, and receiving a first indication of the specified device, a second indication of the data, and a third indication of a size of the data during the monitoring. A new error correction code may be generated in hardware for the data based on the indicated size of the data and an indication may be provided to signal when generation of the new error correction code for a specified number of accesses for at least a portion of the data is complete. Detected errors may be corrected in software based on the newly generated error correction code. The first indication may be a device selection signal and the error correction code generation may be enabled or disabled via an enable signal.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A radio frequency (RF) phase shifter having an RC-CR circuit that includes a first capacitor having a first capacitor node and a second capacitor node and a first resistor coupled between the first capacitor node and a ground. The RC-CR circuit also includes a second resistor having a first resistor node and a second resistor node and a second capacitor coupled between the first resistor node and the ground. The RF phase shifter generates arbitrary phase shift by using a scheme of adding two perpendicular vectors with variable gains (or amplitudes).

Abstract: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to outputs of the photo-diodes in the corresponding column. Parallel processing of the data streams produced by the multiple ADCs improves the bandwidth of the imaging device. The ADCs have one or more capacitors based on a reference capacitor that are configured so that the corresponding capacitors for different ADCs are substantially equal across the CMOS substrate. As such, image variation and streaking across the columns of photo-diodes is minimized or eliminated. The reference capacitors of the ADCs are above a minimum capacitance value, determined by a maximum variation of the reference capacitors across the substrate.

Abstract: A packet voice transceiver adapted to reside at a first end of a communication network and to send and receive voice packets to and from a second packet voice transceiver residing at a second end of the communication network. The transceiver includes a voice encoder, a packet transmitter, a packet receiver, a voice decoder and a far-end echo canceller. The voice encoder receives an ingress audio signal and encodes the audio signal to produce an ingress packet voice signal. The packet transmitter transmits the ingress packet voice signal over the network to the second packet voice transceiver. The packet receiver receives an egress packet voice signal transmitted over the network by the second packet voice transceiver. The voice decoder decodes the egress packet voice signal to produce an egress audio signal. The far-end echo canceller reduces echo that is present in the egress audio signal and that originated at the second end.