Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Abstract: A system and method is provided for scheduling transmissions from a plurality of services operating over a widely distributed communications network. A headend communications device (such as a cable modem termination system) arbitrates bandwidth among a plurality of cable modems configurable for bi-directional communications. The headend grants a bandwidth region to a specified cable modem or assigns contention regions for a group of cable modems. Each cable modem contains a local scheduler that sends requests for bandwidth according to local policies or rules. Upon receipt of a grant from the headend, the local scheduler selects packets to be transmitted to best serve the needs of the services associated with the cable modem. Accordingly, a service requesting bandwidth may not be the service utilizing the grant corresponding to bandwidth request. Nonetheless, the local scheduler manages bandwidth allocation among its local services such that all requesting services eventually receive bandwidth.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A switchboard device and methods of operation of same are disclosed. Embodiments of the invention may provide a flexible means of interconnecting wideband and narrowband communications interfaces, where wideband communications interfaces may transfer low-band data and high-band data, and narrowband communication interfaces may transfer low-band data. Low-band data may be combined and sent to a narrowband communications interface or a wideband communications interface. High-band data may be combined and sent to a wideband communications interface. The low-band data may represent audio signals below a predetermined frequency, while the high-band data may represent audio signals above the predetermined frequency. The predetermined frequency may be, for example, approximately 4 kHz. The spectral mask of the low-band data may meet the spectral mask of G.712. Methods of operating embodiments of the present invention are included.

Abstract: A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

Abstract: A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method, system, and computer program product are provided to convey and maintain information used to synchronize the packetization and burst operations within the network. During session setup, jitter constraints indirectly are used to explicitly communicate a synchronization timing reference. The timing reference is set at the beginning of a phase/period boundary used to service the session. In an embodiment, the announcement of the first grant is used as an explicit indication of the synchronization timing reference value. In another embodiment, the synchronization timing reference value is inferred if a remote device receives contiguous voice grants meeting certain conditions. In an embodiment implementing periodic scheduling, the actual arrival of the first grant is used to infer the synchronization timing reference value.

Abstract: A packet voice transceiver adapted to reside at a first end of a communication network and to send an ingress communication signal comprising voice packets to, and receive an egress communication signal comprising voice packets from, a second packet voice transceiver residing at a second end of the communication network. The packet voice transceiver includes a far-end echo canceller that reduces echo that is present in the egress communication signal. The far-end communicates with other functional components of the transceiver system and adapts its behavior based on the activity of the other functional components.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A one-time programmable memory. The memory has a substrate, a diffused electrode disposed on the substrate, a shallow trench isolation (STI) region formed on the substrate, a insulator formed on the STI region and the substrate, and a second electrode. The insulator separates the second electrode from the diffused electrode. At least a part of the second electrode overlaps at least a part of the STI region.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. The PSE controller also monitors for a Maintain Power Signature (MPS).

Abstract: An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die area is utilized as compared to metal fuses. Additionally, because OTP memories can be implemented as part of standard complementary metal oxide semiconductor (CMOS) processes, the method is less costly and complex than the use of electrically-erasable programmable read-only memories (E2PROMs).

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A system and method are presented for changing physical layer (PHY) parameters in a PHY device of a communications system. New parameters are written to a first-in first-out queue in a serial interface, while the scheduled time for the changeover is written to a control register in the serial interface. When the time for the changeover occurs, the parameters are written to the PHY device via a port of the serial interface.

Abstract: The present invention provides a transmitter architecture operable to cancel non-data-related direct current (DC) components therein. One method to cancel transmitter non-data-related DC offsets includes generating a baseband digital null signal. Then the digital null signal is converted to a pair of differential analog voltage null signals. The pair of differential analog voltage null signals may be converted to a pair of differential analog current null signals. The pair of differential analog current null signals is provided to a pair of matched impedances to generate a pair of voltage signals across the pair of matched impedances. A voltage offset results from comparing the pair of voltages generated across the pair of matched impedances. Then a current offset is determined based on the voltage offset.

Abstract: A traffic prioritization system and method performs a coarse classification of upstream bursts at the physical interface of a wireless communications device. The wireless device monitors and controls communications with a plurality of remote wireless communications devices throughout a widely distributed network, including the Internet. The traffic prioritization system includes a burst receiver that receives and sends the upstream bursts to a classifier. At an appropriate time, the classifier receives the upstream bursts and queries a priority lookup table (LUT) to determine a priority classification. The priority classification is used to separate the bursts into two or more priority levels. The higher priority level is used to designate services having a low tolerance for delay, such as telephony. Upon classification, the upstream bursts are forwarded to one of several priority queues. Each priority queue corresponds to at least one priority level.

Abstract: A method to reduce transmitted output power and the battery consumption is provided. This involves first determining the required output level. The amplitude of the input signal provided to a PA driver may be based on the required output power level. This amplitude may be set by a PGA. A number of cascode bias signals are also provided to the PA driver. These cascode bias signals are based on the required output power level as well. Reducing the cascode bias signals by enabling/disabling circuits within the PA driver allows power consumption of the wireless device to be reduced.

Abstract: A bandpass filter includes a plurality of resonators. An input pin is connected to a first resonator of the plurality of resonators. An output pin is connected to a second resonator of the plurality of resonators. The first and second resonators are magnetically coupled to each other. The first and second resonators are coupled to other resonators using mixed coupling. The other resonators are coupled to each other using electric coupling.

Abstract: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.