Patents Assigned to Broadcom Corporation
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Patent number: 7120411Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.Type: GrantFiled: May 3, 2002Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Hooman Darabi
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Patent number: 7120393Abstract: A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a temperature sensing module that produce accurate voltage level readings may be mapped into corresponding temperature values. A processor, among other actions, adjusts gain level settings based upon detected temperature values. One aspect of the present invention further includes repetitively inverting voltage signals across a pair of semiconductor devices beings used as temperature sensors to remove a common mode signal to produce an actual temperature-voltage curve. In one embodiment of the invention, the circuitry further includes a pair of amplifiers to facilitate setting a slope of the voltage-temperature curve.Type: GrantFiled: August 6, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Arya Reza Behzad, Michael Kappes
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Patent number: 7119726Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.Type: GrantFiled: October 17, 2005Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Minsheng Wang
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Patent number: 7119585Abstract: A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors.Type: GrantFiled: August 27, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Sumant Ranganathan
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Patent number: 7120319Abstract: A versatile data handling apparatus providing multiple alternatives for inputting data is disclosed. The apparatus includes an array of depressible keys, a screen-based input system that is located distinctly from the depressible keys, an optical information sensing component and a visual display to present visual information to a user. The data input activities are coordinated by a computerized data handling system communicatively coupled with the various components.Type: GrantFiled: February 28, 2002Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Arvin D. Danielson, Dennis A. Durbin, David C. Hacker, Jerry L. Walter
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Patent number: 7120405Abstract: The wide bandwidth transceiver includes a receiver section, a transmitter section, and a local oscillation module. The receiver section includes a 1st receiver intermediate frequency (IF) stage, a receiver switch module, and a 2nd receiver IF stage. The 1st receiver IF stage is operably coupled to convert a 1st inbound radio frequency (RF) signal into a 1st inbound IF signal based on a 1st local oscillation of the local oscillation module. The receiver switch module passes either the 1st inbound IF signal or a 2nd inbound RF signal, which have similar carrier frequencies, to the 2nd receiver IF stage. The 2nd receiver IF stage receives the selected signal from the receiver switch module and based on a 2nd local oscillation converts the selected signal into a low intermediate frequency signal. The transmitter section includes a 1st transmitter intermediate frequency (IF) stage, a 2nd transmitter IF stage, a power amplifier and a transmitter switch module.Type: GrantFiled: November 27, 2002Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Ahmadreza (Reza) Rofougaran
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Patent number: 7120203Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.Type: GrantFiled: May 14, 2002Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Jeffrey Bauch, Richard Berard, Christopher R. Pasqualino, Stephen G. Petilli
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Patent number: 7120123Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.Type: GrantFiled: November 9, 2000Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Thomas J. Quigley, Jonathan S. Min, Lisa V. Denney, Henry Samueli, Sean F. Nazareth, Feng Chen, Fang Lu, Christopher R. Jones
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Patent number: 7120399Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.Type: GrantFiled: June 12, 2003Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Shahla Khorram
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Patent number: 7119631Abstract: Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.Type: GrantFiled: May 12, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Jesus Alfonso Castaneda, Qiang (Tom) Li
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Patent number: 7120410Abstract: A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize signal-to-noise ratio of the mixer and to force the mixer to operate well within its linear region when an intermodulation interference component is present. The RF receiver includes a first received signal strength indicator (RSSI_A) coupled to the output of the mixer that measures the strength of the wideband signal at that point. A second received signal strength indicator (RSSI_B) couples after the BPF and measures the strength of the narrowband signal. The LNA gain is set based upon these signal strengths. By altering the gain of the LNA by one step and measuring the difference between a prior RSSI_B reading and a subsequent RSSI_B? reading will indicate whether intermodulation interference is present.Type: GrantFiled: September 28, 2001Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Hong Shi
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Patent number: 7119616Abstract: The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is divided between two legs of the input stage and is higher in the leg that has the higher of the two input voltage levels (in or inb). The devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and is utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices are connected in a cross-coupled configuration. The NMOS current mirrors are utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.Type: GrantFiled: September 14, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Darrin R. Benzer
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Patent number: 7119624Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.Type: GrantFiled: March 30, 2005Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Ramon A. Gomez
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Patent number: 7120155Abstract: A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.Type: GrantFiled: April 6, 2001Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Michael Sokol, William Chien
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Patent number: 7119750Abstract: A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is self-contained inside a housing of the communication card and has an electrical interface for communicating information to and from the computer apparatus. The computer apparatus receives the communication card such that it engages the electrical interface. These contacts automatically connect the communication card to an appropriate antenna, telephone or telephone line. A radio communication card is connected to the appropriate antenna for the type and frequency of the radio. A modem card is connected to a standard telephone line, a cellular phone, or an antenna for a cellular phone if the cellular phone is also disposed within the housing of the modem communication card. Additionally, a switching matrix can be used to connect one set of contacts on a radio card or a modem card to one or more of a plurality of antennas and telephone lines.Type: GrantFiled: September 22, 2005Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Patrick W. Kinney, Ronald L. Mahany, Guy J. West
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Patent number: 7119620Abstract: In an RF communication system, aspects of constant or proportional to absolute temperature biasing for minimizing transmitter output power variation may comprise configuring at least one current source to provide a temperature dependent current, where the current may be constant with temperature or vary proportionally to absolute temperature. A control voltage that may be generated by an operational amplifier may be fed back to control the current source. An input reference voltage may also be generated for the operational amplifier by utilizing PN junction characteristics of at least one bipolar junction transistor. Resistance may be adjusted to allow operation of the current source at a plurality of different supply voltages, including the different supply voltages that may be less than 1.2 volts, for example. Additionally, adjusting the resistance may also allow the current to be constant with temperature or vary with temperature.Type: GrantFiled: November 30, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventor: Michael (Meng-An) Pan
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Patent number: 7120420Abstract: A process of creating incentives for wireless hotspots by a service provider is disclosed. An access point is provided to a wireless hotspot for wireless devices to wirelessly connect to a larger network in a publicly accessible location. Use of the access point for a portable device is authenticated by requesting submission of an account identifier to the service provider and billing data for a user of the portable device for use of the access point is generated. Use statistics are evaluated of the access point of the wireless hotspot by portables devices and an inducement is provided to the publicly accessible location based on the evaluated use statistics.Type: GrantFiled: August 12, 2004Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Jeyhan Karaoguz, Nambi Seshadri
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Patent number: 7120117Abstract: A shared memory packet switching device includes: a shared memory providing a shared memory space; an input logic unit associated with at least one receive port, and being operative to determine whether the associated receive port is saturated by determining whether a number of packets received via the associated receive port and currently stored in the shared memory exceeds a drop threshold value; a packet routing control unit operative to determine a destination one of the transmit ports for each of the received data packets; and an output logic unit associated with at least one of the transmit ports, the output logic unit being communicatively coupled with the packet routing control unit, and being operative to determine whether the associated transmit port is congested by determining whether a number of packets currently stored in the shared memory that are to be transmitted via the associated transit port exceeds a congestion threshold value, and also being operative to generate an associated output fullType: GrantFiled: August 29, 2000Date of Patent: October 10, 2006Assignee: Broadcom CorporationInventors: Yao-Ching Liu, William Dai, Jason Chao
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Publication number: 20060223472Abstract: The present invention relates to a DC offset canceling circuit. In one aspect of the invention, a DC offset canceling circuit with independently configurable gain and roll-off frequency is provided. In one embodiment of the present invention, the DC offset canceling circuit is used in the receive path of a down-conversion wireless receiver. In another aspect of the invention, a method for independently varying the gain and the roll-off frequency of the DC offset canceling circuit is provided. In one embodiment, the method is used to independently operate a gain control scheme and a DC offset cancellation strategy in a DC canceling circuit.Type: ApplicationFiled: March 30, 2006Publication date: October 5, 2006Applicant: Broadcom CorporationInventors: Amit Bagchi, Rohit Gaikwad
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Publication number: 20060220738Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second programmable gain amplifiers (PGAs). The first PGA is tuned to have a resonant frequency that is less than an operating frequency of the first PGA. The second PGA is tuned to have a resonant frequency that is greater than an operating frequency of the second PGA. A magnitude response at an output of the first PGA and a magnitude response at an output of the second PGA combine to provide a substantially linear magnitude response across a frequency range that includes the operating frequency of the first or second PGA. According to an embodiment, the first and second PGAs have the same operating frequency.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Applicant: Broadcom CorporationInventor: Meng-An Pan