Abstract: A signal strength indicator circuit that includes a first amplifier configured to receive a first input signal from a first mixer and a second input signal from a second mixer;. The circuit also includes a second amplifier configured to receive a first set of differential inputs from the first amplifier. The circuit further includes a third amplifier configured to receive a second set of differential inputs from the second amplifier stage. Even further, the circuit includes an output port for emitting an output signal that is a rectified combination of the first input signal and the second input signal. Also, a method of processing signals input into a signal strength indicator circuit.
Abstract: A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.
Abstract: Decoding time stamps (DTSs) and presentation time stamps (PTSs) are used in fine granularity scalability (FGS) coding during MPEG-4 video coding. An input video is encoded in an FGS encoder into a base layer bitstream and an enhancement bitstream. The bitstreams are provided over a variable bandwidth channel to an FGS decoder. The DTSs and the PTSs are selected during encoding as to conserve memory during FGS decoding. The video object planes (VOP) in the bitstreams include base VOPs and FGS VOPs, and may also include fine granularity temporal scalability (FGST) VOPs. The FGS VOPs and the FGST VOPs may be organized in the same layer or in different layers. The base VOPs are combined with the FGS VOPs and the FGST VOPs to generate enhanced VOPs.
Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.
Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.
Abstract: A method for coordinating multiple protocols using a shared communication medium by a plurality of networks begins by exchanging packets between a plurality of communication devices to obtain access to the shared communication medium, wherein the packets are formatted in accordance with at least one of the multiple protocols of at least one of the plurality of networks. The method continues by transmitting by at least one of the plurality of communication devices within another one of the plurality of networks via the shared communication medium.
Type:
Application
Filed:
June 26, 2006
Publication date:
November 2, 2006
Applicant:
Broadcom Corporation, a California Corporation
Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.
Abstract: A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.
Abstract: A continuous time filter having a first stage and a second stage. A first stage adjusts a bandwidth of the signal. A second stage adjusts bandwidth of the signal subsequent to the first stage. Each stage includes a first capacitor with a first capacitance and a second capacitor with a second capacitance for providing uniform step sizes for bandwidth adjustment. The continuous time filter may include a plurality of cascaded stages including the first stage and the second stage. In addition, a bandwidth adjustment across the first stage and the second stage may be controlled using a semi-interleaved thermometer coding to achieve a cascaded effect for the bandwidth adjustment.
Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.
Abstract: The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output transistors. By proper setting of gate voltage time constants and overlap of NMOS and PMOS “on” times, a desired output slew rate is accomplished, having a smooth output transition, without generation of shoot-through current. The programmable slew rate driver includes a first driver transistor coupled between the first supply voltage and output, a second driver transistor coupled between the second supply voltage and output, a plurality of upper transition blocks coupled in parallel and a plurality of lower transition blocks coupled in parallel between the first and second supply voltage. The rates of change and overlap of the gate voltages are in turn substantially determined by the resistance of the lower transition control blocks and the capacitance of the gate of the second driver transistor.
Abstract: A circuit includes a plurality of circuit components formed on a semi conductive substrate die and a bond wire. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.
Abstract: Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.
Type:
Grant
Filed:
October 31, 2002
Date of Patent:
October 31, 2006
Assignee:
Broadcom Corporation
Inventors:
Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
Abstract: An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity.
Abstract: A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.
Abstract: The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate.
Abstract: A method for adjusting a programmable mixer of a local oscillation module to reduce local oscillation leakage begins by determining at least one of: DC offset of an input signal of the programmable mixer and process mismatches between a first mixing stage and a second mixing stage. The method continues by determining operational characteristics mismatch between the first mixing stage and the second mixing stage based on the at least one of the DC offset and process mismatches. The method continues by generating a control signal to substantially compensate for the operational characteristics mismatch. The method continues by providing the control signal to a compensation module, wherein the compensation module modifies operational characteristics of at least one of the first and second mixing stages based on the control signal such that the operational characteristics of the first mixing stage substantially equals the operational characteristics of the second mixing stage.
Abstract: The present invention is directed to circuits and methods to efficiently conduct scan testing of integrated circuits in which first level packaging is varied to provide different versions of the integrated circuit. An integrated circuit is provided that includes at least one bond pad test circuit. The bond pad test circuit is coupled between a bond pad and functional components within an integrated circuit. In one embodiment, the bond pad test circuit includes a multiplexer and a D flip-flop in which the D input of the flip-flop is coupled to a bond pad. In another embodiment, the bond pad test circuit includes a multiplexer and a D flip-flop in which the D input of the flip-flop is coupled to the output of the multiplexer. A method for scan testing using an integrated circuit with a bond pad test circuit is also provided.
Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
Abstract: An apparatus and for enabling functionality of a component, wherein the apparatus includes an identification module having an identification number stored therein, and a hash function module in communication with the identification module. A host is provided and is in communication with the identification module, and a guess register in communication with the host is provided. An encryption module is provided and is in communication with the guess register, and a public key module in communication with the encryption module is provided, wherein the public key module has a public key stored therein. A comparator in communication with the encryption module and the hash function module is provided, such that the comparator may compare a first bit string to a second bit string to generate a function enable output for the component.