Abstract: An inductor circuit includes a magnetic interface generator that generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna is printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to effect performance of an inductor that printed on the second layer.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: An apparatus and process for relabelling and redirecting at least some of the read transaction data frames and the write transaction write data and transfer ready frames in a network so as to bypass a storage manager and pass directly between the client and a storage device via a switch. This eliminates the storage manager as a bottleneck. Some embodiments redirect every read and write transaction, and others redirect only large transactions, or only ones not stored in cache or when latency gets too high. Redirection is accomplished by transmission from the storage manager to a switch redirection commands that contain old and new address data. When a frame to be redirected comes in, its address is compared to the old address data. If there is a match, the new address data is substituted and the frame is passed to a conventional routing process to be routed so as to bypass the storage manager.

Abstract: A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Abstract: A signal power detector includes an input coupling circuit, a rectifying operational amplifier, a comparator, and a charge pump. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal. The comparator is operably coupled to compare the peak value of the signal with an output peak value to produce a comparison value. The charge pump operably coupled to convert the comparison value into a corresponding current that represents the output peak value.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A buffer circuit comprised of two matched stages is provided. The first stage develops a replica voltage that is used in the second stage as the input to a wide-band amplifier. The combination of the two feedback loops in the circuit result in improved linearity. The first amplifier dominates for moderate frequencies while the second amplifier takes over for high frequencies.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: A transmitter includes a dual mode modulator and an amplifier coupled to the dual mode modulator. The dual mode modulator implements a linear modulation scheme during a first mode of the modulator to produce a variable envelope modulated signal. The dual mode modulator implements a non-linear modulation scheme during a second mode of the modulator to produce a constant envelope modulated signal. The amplifier is biased as a linear amplifier during the first mode of the modulator and is biased as a non-linear amplifier during the second mode of the modulator. A feed-forward connection between the dual mode modulator and the amplifier is used to indicate a change in modulation mode and to adjust the bias of the amplifier. A power of the constant envelope modulated signal is increased such that an operating point of the amplifier remains substantially constant during the first and second modes of the modulator.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.

Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

Abstract: Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

Abstract: Techniques for controlling and managing network access are used to enable a wireless communication device to selectively communicate with several wireless networks. A portable communication device constructed according to the invention can communicate with different networks as the device is moved through the areas of coverage supported by the different networks. As a result, the device can take advantage of services provided by a particular network when the device is within the area of coverage provided by that network. Thus, the device can selectively switch to networks that provide, for example, high speed Internet access, different quality of service, low cost service and/or different services (e.g., voice, data, multimedia, etc.). A multi-mode controller in the device may be used to alternately poll different networks to determine whether the device is within the area of coverage of a network and to selectively establish communications with those networks.

Abstract: A network device, which includes a plurality of network ports, a switching unit, a data classification unit, and a rate control unit, is provided. The plurality of network ports is configured to send and receive input data packets. The switching unit is coupled to the plurality of network ports and is configured to switch input data packets from a first port to a second port. The rate control unit is coupled to the switching unit and configured to control a data rate provided to each port of the plurality of network ports. The data classification unit is coupled to the switching unit and to the rate control unit. The data classification unit is configured to classify data packets based on their contents and output a classification to the rate control unit. The rate control unit is configured to perform rate control for input data packets based on the classification of each data packet.