Patents Assigned to Broadcom Corporation
  • Patent number: 7109799
    Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Guangming Yin, Jun Cao
  • Patent number: 7109798
    Abstract: For a high frequency buffer, a high frequency output path may be isolated from a low frequency feedback path using a common mode feedback loop. The common mode feedback loop may be utilized to adjust an output DC level. The common mode feedback loop may comprise a first differential amplifier and a first transistor. An output of the first differential amplifier may be coupled to an input of the first transistor, and the low frequency feedback path may communicate the output DC level from an output of the first transistor to a first input of the first differential amplifier. A reference voltage may be communicated to a second input of the first differential amplifier, and this reference voltage may be variable. The first differential amplifier may be adapted to compare the inputs and generate a control voltage, which may be utilized to adjust the output DC level.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventor: Hooman Darabi
  • Patent number: 7110309
    Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Esin Terzioglu, Morteza Cyrus Afghahi
  • Patent number: 7111208
    Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Tuan M. Hoang, Hongtao Jiang
  • Patent number: 7111104
    Abstract: A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking bus connects the first repeater and the second repeater and is configured to relay status signals between the first and said second repeaters.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Xi Chen, Brian Chang
  • Patent number: 7111117
    Abstract: A method to expand a RAID subsystem from a first array of disk drives to a second array of disk drives. The first array includes a set of data disk drives storing old data and spare space, and the second array includes the first array and at least one new disk drive. First, the old data are distributed among the set of data disk drives and at least one new disk drive while, at the same time, new data are mapped to the spare space. Upon completion of the distribution, the new data are copied from the spare space to the set of data disk drives and at least one new disk drive to enable concurrent expansion of the first array while accessing the old and the new data.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Chris R. Franklin, Jeffrey T. Wong
  • Patent number: 7110398
    Abstract: A method and system for creating an ethernet-formatted packet from an upstream DOCSIS packet. The upstream packet is first received along with packet characteristic data that is contained in physical layer prepend data and in the packet header. A packet tag is then created, based on the packet characteristic data. The packet characteristic data includes identifiers for the transmitting remote device and the channel over which the transmission is sent. Packet characteristic data also includes information about the physical characteristics of the transmission signal, such as the power level and time offset. The packet characteristic data also includes administrative information, such as the minislot count at which the packet is received and whether the packet was received in contention. The packet tag is appended to the payload of the upstream packet. Also appended to the payload is an encapsulation tag, and source and destination address headers. The result is a packet in an ethernet format.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Gerald Grand, Niki R Pantelias, R. Jeff Lee, Michael Zelnick, Francisco J Gomez
  • Patent number: 7110469
    Abstract: A self-calibrating transmitter includes an up-conversion mixing module, summing module, calibration determination module, and a calibration execution module. The up-conversion mixing module is operably coupled to mix an I component of a base-band signal with an I component of a local oscillation to produce a mixed I signal and is also operably coupled to mix a Q component of the base-band signal with a Q component of the local oscillation to produce a mixed Q signal. The summing module sums the mixed I signal with the mixed Q signal to produce a modulated radio frequency (RF) signal. The calibration determination module is operably coupled to produce a calibration signal, which it generates by interpreting the local oscillation and the modulated RF signal. The calibration execution module is operably coupled to calibrate the DC level of the I and/or Q component of the base-band signal, and/or the gain of the I and/or Q component of the base-band signal based on the calibration signal.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Hong Shi, Henrik T. Jensen
  • Patent number: 7111226
    Abstract: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Patent number: 7109947
    Abstract: A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Nicolaos G. Alexopoulos, Harry Contopanagos, Chryssoula Kyriazidou
  • Publication number: 20060203901
    Abstract: An apparatus and method for correcting IQ imbalance are presented. An exemplary receiver for processing I and Q signals from a tuner includes: a non-decision directed (NDD) imbalance canceller coupled to receive the I and Q signals, and a decision directed (DD) imbalance canceller coupled to the non-decision directed imbalance canceller. The DD imbalance canceller converges after the NDD imbalance canceller converges, so as to correct IQ imbalances in the receiver. An exemplary method for processing I and Q signals from a tuner includes: (a) converging a NDD imbalance canceller to correct a majority of IQ imbalances, and (b) subsequently converging a DD imbalance canceller to correct a remainder of IQ imbalances not corrected in step (a). The apparatus and method correct frequency-dependent and frequency-independent IQ imbalances.
    Type: Application
    Filed: January 19, 2006
    Publication date: September 14, 2006
    Applicant: Broadcom Corporation
    Inventors: Loke Tan, Hanli Zou, William Ngai
  • Publication number: 20060205370
    Abstract: A mixer produces an improved output signal during frequency translation of an input signal using a local oscillator (LO) signal. The mixer includes five component mixers connected in parallel. Each component mixer uses a phase-shifted version of the LO signal for frequency translation to produce a component output signal from the input signal. The component output signals are scaled according to corresponding gain factors and combined to form the output signal. When the mixer is used in a receiver, the phases of the component LO signals and the gain factors are configured to substantially cancel overlapping baseband versions of component input signals located at the third, fifth, seventh and ninth harmonics of the LO frequency. When used in a transmitter, the same phase and gain factor configurations substantially cancel third, fifth, seventh and ninth harmonics within the output signal.
    Type: Application
    Filed: October 31, 2005
    Publication date: September 14, 2006
    Applicant: Broadcom Corporation
    Inventors: Takayuki Hayashi, Danilo Manstretta
  • Publication number: 20060203424
    Abstract: A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.
    Type: Application
    Filed: January 4, 2006
    Publication date: September 14, 2006
    Applicant: Broadcom Corporation
    Inventors: Henry Chen, Akira Ito
  • Publication number: 20060203898
    Abstract: A method for estimating electrical length of a loop in a digital subscriber line (DSL) system begins by estimating an electrical length of a loop for each of a plurality signals based on a known power level of the plurality of signals, a known frequency for each of the plurality of signals, and a received power level for each of the plurality of signals. The method continues by processing the plurality of estimated electrical lengths in accordance with a function corresponding to characteristics of the loop to produce a determined electrical length.
    Type: Application
    Filed: May 9, 2006
    Publication date: September 14, 2006
    Applicant: Broadcom Corporation, a California Corporation
    Inventors: Vladimir Oksman, Raphael Rahamim
  • Patent number: 7106787
    Abstract: A system and method for acquiring a transmitted spread-spectrum signal uses a matched filter configuration that is preferably employed as a Stage 2 filter in the second phase of an initial signal acquisition procedure performed in the receiver. In operation, a Stage 1 filter matches a sequence which is repeated a number of times according to a second sequence within a secondary synchronization sub-channel of the spread-spectrum signal. The Stage 2 filter of the invention then filters the output of the Stage 1 filter in order to recover a secondary synchronization code. The Stage 2 filters the output of the Stage 1 filter using three matched filters of its own. The first and second filters sample different taps of a sequence output from the Stage 1 filter. The third filter samples a predetermined number of taps overlapping taps for the first and second filters in a way that resolves ambiguities with respect to the identification of the sequence.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventors: Li Fung Chang, Kapil Chawla, Nelson Sollenberger
  • Patent number: 7107080
    Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, it is processed to produce a null page pattern. The wireless terminal may then enter a sleep mode or reduced functionality mode for a predetermined period of time. The wireless terminal awakes from the sleep mode to receive additional encoded paging bursts. Processing the additional encoded paging bursts produces a processed encoded paging burst, which is compared to the null page pattern. When compared favorably, the encoded paging burst is considered a null page, allowing the wireless terminal to re-enter the sleep mode without fully decoding the paging burst.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventors: Ronish Patel, Nelson Sollenberger
  • Patent number: 7107511
    Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Kelly Brian Cameron, Hau Thien Tran
  • Patent number: 7106122
    Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventor: Arya Reza Behzad
  • Patent number: 7106734
    Abstract: A network switch for network communications includes a first data port interface, supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supporting a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface communicating with a CPU, an internal memory, a memory management having an external memory interface, and a communication channel are provided. A plurality of lookup tables having address resolution lookup/layer three lookup, rules tables, and VLAN tables are provided. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses and a synchronization process per entry is provided.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventors: Shiri Kadambi, Shekhar Ambe
  • Patent number: 7107429
    Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: September 12, 2006
    Assignee: Broadcom Corporation
    Inventors: Stephen Barlow, Timothy Ramsdale, Robert Swann, Nel Bailey, David Plowman