Abstract: Circuits and methods to enhance scan testing by controlling clock pulses that are provided to memory devices within an integrated circuit are provided. An integrated circuit is provided that includes a scan testing clock control circuit and a memory bypass enable contact point. The scan testing clock control circuit enables control of a clock input signal to one or more memory devices within the integrated circuit. In one embodiment the scan testing clock control circuit includes a latch, and two AND gates. A scan test mode input and a memory bypass enable input are used to determine whether the memory will be permitted to receive a clock signal. Methods for scan testing using a scan testing clock control circuit are also provided.

Abstract: Systems and methods that protect transport stream content are disclosed. The system may include a first module and a second module, the first module having a common interface. The second module is coupled to the first module via the common interface. In one embodiment, the first module is a set top box, and the second module is a conditional access card. In one example, the first module demodulates an incoming transport stream, copy protection encrypts the demodulated transport stream and passes the copy protection encrypted transport stream to the second module via the common interface. The second module copy protection decrypts the transport stream received from the first module, conditional access decrypts at least some of packets of the transport stream that were conditional access encrypted, copy protection encrypts the transport stream and passes the copy protection encrypted transport stream to the first module via the common interface.

Abstract: A video and graphics system provides square graphics pixels to blend images having 640×480 pixels, such as graphics images provided by some set top boxes and intended to be displayed at a 12.27 MHz display sample rate, with images having 704×480 pixels, such as ITU-R 601 compliant images such as NTSC SDTV images, having oblong pixels and displayed at a 13.5 MHz display sample rate. A sample rate converter including a multi-phase-multi-tap filter is used to generate square pixels. The multi-phase-multi-tap filter provides a good balance of sharpness, smoothness, anti-aliasing and reduced ringing. The multi-phase-multi-tap filter can also be used to convert images having 320×480 pixels to images having 704×480 pixels. The multi-tap filter can be used for scan rate conversion of graphics or video images for HDTV or SDTV applications.

Abstract: A varactor-based ring oscillator to produce an output signal and method therefore are disclosed. The ring oscillator includes a first phase shift circuit having a first pole. The ring oscillator also includes a second phase shift circuit having a second pole and a third phase shift circuit having a third pole. The output of the third phase shift circuit is cross-coupled to the input of the first phase shift circuit. A phase shift circuit of the ring oscillator includes a pole that has a varactor and generates phase shift for the phase shift circuit. The varactor can be adjusted or varied to tune, the phase shift, the phase shift circuit and the frequency of the oscillator. If the varactor is in the final phase shift circuit of the oscillator, the varactor is coupled to a diode that supplies voltage to the varactor. A voltage control signal is applied to the pole, and to the oscillator, to generate the output signal having a specified frequency.

Abstract: A system provides dual use of a general purpose input/output (I/O) line. In an embodiment, the system comprises a controlling circuit having a dual purpose I/O line that is selectively operable in a serial transmit mode or an I/O mode. A first circuit that receives a serial data stream when the controlling circuit operates in the serial transmit mode is coupled to the I/O line. A second circuit that generates and transmits a signal when the controlling circuit operates in the I/O mode is also coupled to the I/O line. Finally, a third circuit is disposed between the second circuit and the I/O line. In an embodiment, when the controlling circuit operates in the serial transmit mode, the third circuit maintains the second circuit in an idle state, and when the controlling circuit operates in the I/O mode, the third circuit permits the second circuit to transmit the signal to the controlling circuit.

Abstract: An LED interface circuit provides connection options for one or more types of LEDs. In an embodiment, the circuit includes an input node that receives an LED control signal, and an output that has a first output node, and a second output node. A driving circuit is disposed between the input header and the output. The driving circuit has a non-inverted input node and an inverted output node. In an embodiment, the inverted output node is capable of sinking current. The non-inverted input node is coupled to the input header and to the first output node, while the inverted output node is coupled to the second output node. The output of the LED interface circuit is capable of driving a plurality of different types of LED displays.

Abstract: A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: In a data communication system, a transmitter of a modem, for example, uses a single scrambler to operate in a data communication mode and in a non-data mode. During the data communication mode the scrambler is used to scramble data for communication by the transmitter. During the non-data mode, the scrambler is used to generate a non-data mode signal for communication by the scrambler. The modem may be an ADSL modem, for example, in which case the data communication mode is SHOWTIME while the non-data mode may be Q-mode.

Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

Abstract: A process of detecting and communicating alarm events by a security system is disclosed. Sensors in communication with the security system are monitored, where specific changes in outputs of the sensors indicate an alarm event. It is determined whether a landline communication medium connecting the security system with a monitoring headquarters is active, when the alarm event is detected. Data, indicating the alarm event, is sent over the landline communication medium to the monitoring headquarters when the landline communication medium is determined to be active. Also, data, indicating the alarm event, is sent over a wireless communication medium to the monitoring headquarters when the landline communication medium is not determined to be active.

Abstract: Systems and methods that protect heading information using a dedicated cyclic redundancy check (CRC) are provided. In one embodiment, a method that transmits a data packet may include, for example, one or more of the following: creating a header CRC by performing a CRC process on header information, the header information indicating where to place data information; separately creating a data CRC by performing the CRC process on the data information; and forming a data packet including, for example, the header information, the header CRC, the data information and the data CRC.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: Certain embodiments of the invention provide a method and system for allocating memory during encoding of an uncompressed information stream. A method for allocating memory during encoding of a uncompressed information stream may include allocating at least a portion of a device memory for storing at least one of an operating data corresponding to the uncompressed information stream and an operating code corresponding to at least one of a plurality of compression algorithms. At least one of the operating data and the operating code may be stored in at least a portion of the allocated device memory. The method may provide selecting at least one of the compression algorithms and encoding at least a portion of the operating data using the selected compression algorithm, resulting in the creation of a compressed information stream.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: A method of and apparatus for optimizing signal transformation from a twisted pair transmission line to a combination transmitter and receiver for a frame-based communications network, the transmitter having a transmit output pair port for transmitting signals onto the frame-based communications network over the twisted pair transmission line, the receiver having a receive input pair port for receiving signals from the frame-based communications network over the twisted pair transmission line. A transformer is coupled between the twisted pair transmission line and each of the transmit output pair port and the receive input pair port. The transformer has a coil across the twisted pair, a transmit coil across the transmit output pair port, and a receive coil across the receive input pair port. A transfer ratio between the transmit coil and the coil across the twisted pair is optimized for transmitting signals.

Abstract: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in the network device, where the at least one master is connected to the at least one high speed docking station. The master is configured to handle and process data received by the at least one media port and passed to the master through the at least one high speed docking station. The network device is configured to handle media ports of different media types. Thus, the device can handle data received through different media ports that have different media types with the same master, making the network device easily configured to meet a customer's needs.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.