Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.

Abstract: A low power supply band-gap current reference includes a 1st P-N junction device, a 2nd and P-N junction device, a 1st current source, a 2nd current source, a 1st resistor, a 2nd resistor, a 3rd resistor, an operational amplifier, and a current mirror. The 1st and 2nd P-N junction devices are operably coupled to the 1st and 2nd current sources, respectively. The 2nd P-N junction device is a larger device than the 1st P-N junction device. The 2nd resistor is operably coupled in parallel with the 1st P-N junction device and the 2nd resistor is coupled in series with the 2nd P-N junction device. The 3rd resistor is coupled in parallel with the series combination of the 2nd resistor and 2nd P-N junction device. The operational amplifier is coupled to control the 1st and 2nd current sources based on the voltage imposed across the 1st and 2nd resistors. The current mirror is operably coupled to mirror the current of the 1st and/or 2nd current source to provide a band-gap reference current.

Abstract: A method and related computer program product of obtaining temporary conventional memory usage in BIOS. The method and program product comprises disabling processor interrupts, saving a predetermined amount of system memory to a temporary storage location outside system memory, using the predetermined system memory space for BIOS specific needs, restoring the predetermined amount of system memory from the temporary storage location to the predetermined system memory space, and then re-enabling the processor interrupts.

Abstract: A number of features for enhancing the performance of a cable transmission system, in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend, are presented. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: A system for spur cancellation comprises an input, an output, a memory, and a summer. A value corresponding to an energy level of a spur is stored in the memory. The summer is configured to receive an input signal from the input, to receive the value from the memory, to subtract the value from the input signal, and to convey an output signal to the output. The output signal is a difference of the value subtracted from the input signal.

Abstract: A method and system for combing requests for data bandwidth by a data provider for transmission of data over an asynchronous communication medium is provided. A headend receives one or more bandwidths requests from one or more cable modems via upstream communication. A scheduler then combines one or more bandwidths requests from the same cable modem to create a single data burst bandwidth. The headend then grants the data burst bandwidth to the appropriate cable modem via downstream communication.

Abstract: The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a number of factors affect the gain accuracy of the DAC. The present invention provides a circuit architecture to reduce the variation in these factors to ensure the accuracy of the output power of a DAC. The architecture comprises a bandgap portion, replica circuit and a DAC. The bandgap portion of the architecture provides a constant voltage, while the replica circuit provide a correct current to drive the DAC.

Abstract: A multi-frequency clock stretching system is provided. The multi-frequency clock stretching system includes a stretch pulse generator that generates a stretch pulse signal and a multi-frequency clock generator that produces a set of different frequency clock signals in which the clock signal pulses of the set of different frequency clock signals can be stretched as a function of the stretch pulse signal. A data processing system is also provided that includes a data processing portion and a multi-frequency clock stretching system. When the data processing portion recognizes that a clock adjustment is needed, the data processing portion provides a control signal to the multi-frequency clock stretching system that stretches the pulses of clock signals serving as inputs to the data processing portion to better align the pulses and improve system performance.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: During start-up of a circuit having a high voltage supply and a low voltage supply, a backup bias generator (BBG) is used to avoid burnout and exceeding a breakdown voltage. The high voltage supply is powered on before the low voltage supply. The BBG generates bias in response to the high voltage supply being powered on. Once the low voltage supply is powered on and is stable, the BBG is shut down so that it does not interfere with normal operation of the circuit. The circuit can be separated into high and low supply domains without breakdown issues during power start-up, allowing for power and area optimization.

Abstract: A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate and the conductive trace. A first capacitance exists between the conductive trace and the substrate and a second capacitance results between the conductive trace and the substrate due to the presence of the element. The second capacitance is in series with the first capacitance, thereby reducing an effective capacitance between the conductive trace and the substrate.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: Multi-tuner receivers with cross talk reduction are disclosed. In one embodiment, a multi-tuner receiver with cross talk reduction includes a low noise amplifier, a set of interstage filters and a set of corresponding tuners. In an alternative embodiment, a multi-tuner receiver with cross talk reduction includes a passive splitter, a set of interstage filters and a set of corresponding tuners. The interstage filters can be low-pass, high-pass or band-pass filters depending on the particular frequency range of interest. Typical embodiments can have two or three tuners, however, the invention applies to multi-receiver tuners with more than three tuners. The multi-tuner receivers can be used within television, cable set top boxes and other devices that receive multiple video signals.

Abstract: A network device includes a first switch, a second switch, and a CPU. The first and second switches each include a group of ports numbered by a numbering scheme, a rate control logic for performing rate control functions related to switching data packets between the network ports, and a local communications channel for transmitting messages between the group of ports and the rate control logic. Each switch is configured to generate rate control messages based on data packet traffic to its group of ports. The CPU is coupled to the first switch and the second switch and configured to control the first switch and the second switch. A first link port of the first switch is coupled to a second link port of the second switch, and the first link port and the second link port are configured to relay the rate control messages to each other.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.